Implementing IDL streaming for FlexRIO in python API

[Dorino]

Hello,

I am using a 5764 FlexRIO digitizer to acquire pulse signals from other instruments.

For my project, I need to be able to implement everything in python, but the getting started examples for the 5764 uses IDL streams in their VIs.

Is it possible to utilize these IDL streams inside the python API, or is it limited to FIFO control like the API website says. If so, is there a efficient work around to acquiring signals?

Thank you.

[Terry_ALE]

Regardless of deployment, my recommendation is to always develop using LabVIEW and LabVIEW FPGA.  This allows you to better test and validate the bitfile created.  The debug tools in LabVIEW are more comprehensive.

For deployment, see https://forums.ni.com/t5/NI-Linux-Real-Time-Discussions/Introducing-the-FPGA-Interface-Python-API/td...

I am aware of the FlexRIO IDLs being used but not sure if they have python equivalents.

[Dorino]

Hi Terry,

Thank you for your response.

I typically develop/debug using labview and then transfer over to python. For example, I am using a 7976R for pulse generation and have successfully implemented that with the nifpga API. I am familiar with the link you posted, however they only seem to go as far as allowing implementation of a FIFO. I couldnt find any support for IDLs.

I guess my question really is: is it possible to implement a simple acquisition without all the IDL implementation in these FlexRIO devices? That would make it usable with the python API.

Sincerely,

Dorino

[Terry_ALE]

Can you expand on your steaming needs?

[Dorino]

Hi Terry,

That's the thing, I'm not really sure if I need streaming. The shipped example included the streaming implementation.

Essentially, I need the 5764 to start acquiring after receiving a trigger and then the host VI to read the acquired signal. I couldn't find any simplified examples, so I am trying to build up piece-by-piece with the FIFO. It's my first time working with concepts like this, so I wasn't exactly sure what was necessary and what could be removed (such as the stream portions).

Thanks,

Dorino

[Terry_ALE]

All four channels at their full rate of 1 GS/second?  How long is the acquisition after a trigger?  Any pre-trigger?  Built in level trigger is ok?

[Dorino]

Hi Terry,

Currently, I am only using one AI channel @ 1GS/s, acquisition is typically 2-3 us after a trigger. No pre-triggers. I am trying to use a digital edge (rising) trigger to initiate acquisition.

Sincerely,

Dorino

[Terry_ALE]

The read API function is pulling from the example's DMA-FIFO.  Could you remove that function and instead call a read FIFO (from the Host)?

[Dorino]

Hi Terry,

I apologize for the late reply. 

Ultimately, I don't really need the waveform transferred to the host, I just need to acquire the data on the AI channel, perform some control logic, and output the number of times the acquired signal rises above a certain voltage level. This means I don't really the API, and if I wanted to read the data on the host, I could definitely use the FIFO like you suggested.

I'm slowly figuring out how to work around the IDL and realizing what I don't need.

Thank you for you helpful input.

Dorino

[Terry_ALE]

It is tricky.  When using these cards, we mostly built our own FPGA and Host code.  Sometimes we did have to go back to the shipping example to understand things such as TClk.

Is this for only one card with no plans for more cards or multi-card synchronization?