NI VeriStand Add-on: FPGA XML Builder Node
The VeriStand FPGA XML Builder add-on allows users to simplify FPGA VIs being developed for use with NI VeriStand. Traditionally, when creating an FPGA VI for use with NI VeriStand, the user had to bit pack all of the inputs and outputs of the system, as well as create the .fpgaconfig XML file that described the bitfile. The VeriStand FPGA XML Builder Node is a configuration based node which allows the user to specify channels to be sent and received from VeriStand, configure those channels, then automatically generate the necessary XML file for VeriStand. The node then internally handles the bitpacking of the channels and sends/receives the necessary packets using the DMA FIFOs to VeriStand.
After installing the VeriStand FPGA XML Builder node, and used in conjunction with the NI VeriStand FPGA-Based I/O Interface Tools, users can easily create FPGA VIs for use with NI VeriStand. You can add the node to the template's block diagram from the NI VeriStand FPGA Support » FPGA XML palette when in the FPGA context. Then expand the node for the number of I/O you'll be communicating with, configure your channels, and generate the XML configuration file.
A more detailed walk-through of implementing the FPGA XML Builder node is attached to this document.
To install the FPGA XML Builder Node, complete the following steps:
VeriStand 2013 SP1
Veristand 2013 & VeriStand 2014+
All attempts have been made to provide an add-on compatible with the NI VeriStand shipping examples. The nature of some add-ons requires additional software or hardware to function.
This add-on was created for use with NI VeriStand 2013+. To use this add-on you must have the following software installed:
This Add-On provides examples for implementing the node. After installation, these examples can be found at:
<LabVIEW>\examples\NI VeriStand Add-On-FPGA XML Builder Node
This add-on is provided "as is" and is not officially supported by National Instruments.
If you encounter a problem with this add-on, or if you have suggestions for a future revision, please post to the forum for this add-on here: VeriStand FPGA XML Builder Node Feedback Forum. You must use this feedback forum for support. Do not call National Instruments for support for this add-on.
A very useful add-on. Well done!
Went from nothing to finished FPGA VI and XML file in half an hour. Really great!
Hello I have a question regarding this addon.
I tried to install the addon to LabVIEW 2013 but the VIPM said the add on doesn't support the LV 2013.
The HILS system is running now so I don't want to upgread to LV 2014 or 2015 for now.
Is there any way to install the addon to LV 2013 ?
Thank you for your help.
FSE @ NI Japan
The package is compatible with LabVIEW 2013, but you likely need to install VIPM 2014 since the package was built with VIPM 2014. You're likely encountering the issue described here.
Thank you for the quick response. I will try to upgrade VIPM.
thanks for your help.
This add-on is very useful but I found a problem.
It seems that splitting the data written by VeriStand is incorrect.
I want to send reproducible code to you.
Would you contact me by e-mail?
Regarding Known Issue #5 - I believe I see the bug, but am unsure of the correct solution. It appears that, when selecting a numeric as an output, you set a Boolean to true in the "Create Index Array for Numeric Output" VI. If there are no numerics, this Boolean is set to false. Then, in the "Create and Wire Index for Unpack Booleans" VI, you use that previous Boolean output as an input named Add Chunk? This appears to choose whether to create a new feedback node or use one previously created. Perhaps this would work if the condition on that case structure was "If Add Chunk? is TRUE OR the feedback node refs array is EMPTY, then create a new feedback node".
When I double click on the node I only see the first 4 signals that are mapped. All I am doing is measuring PWM Input frequency and Duty cycle which are 64 but unsigned numeric. Only the first 4 shows up and I get the error codes 1055 and 1136 as shown below. I have also attached a snapshot of the code. Any suggestions?
Time: 2:16 PM
Error Source: Property Node in Double Click Tree Read Tree subVI.vi->Node Configuration.vi->FPGA XML.xnode:OnDoubleClick2.vi->FPGA XML.xnode:OnDoubleClick2.vi.ProxyCaller
Time: 2:19 PM
Error Source: Property Node (arg 1) in Double Click Build Tree SubVI.vi->Node Configuration.vi->FPGA XML.xnode:OnDoubleClick2.vi->FPGA XML.xnode:OnDoubleClick2.vi.ProxyCaller
Property Name: <b>Active Item:Tag</b>
When adding a parameter to an FXP channel, the XML builder node inserts the parameter section after the <FXPWL> and <FXPIWL> sections in the .fpgaconfig file as shown.
When selecting the .fpgaconfig file in the System Explorer, you will receive the following Error -2628.
Workaround: Manually place the parameters section <Parameters> ahead of <FXPWL> and <FXPIWL> sections in the .fpgaconfig file as shown.