Hi David,
Your VI looks good to me. The VI is straightforward and the result is correct. I only did a little changes listed below:
1. For FPGA VIs, I strongly recommend using the Timed Loop instead of the While or For Loop if possible. That doesn't impact the resulting values and the number of iterations keeps the same. But the Timed Loop can ensure that each loop iteration consumes exactly one clock cycle (of the hardware timing source and is normally 40M Hz). While the While and For Loop may use at least 4 cycles more than the Timed Loop in each iteration, depending on the content in the loop. However, there're many functions that cannot be placed inside the Timed Loop. (You can find the restrictions in the on-line help or manual files). But your VI can still use the Timed Loop without any problem.
2. The VI can run endlessly if the input value is zero. I added a comparison in the loop and stopped the iteration when all input bits were checked.
3. The output type has the same fractional word length as the Input (i.e.16-bit). I just want to remind you that if you want to keep all precision of the Input, you'll need to make the output word length equal to the (Input's fractional word length + Input's integer word length - 1 = Input's word length - 1). In order not to lose the LSBs of the Input during right shift, you also need to lengthen the fractional word length of the Input by (Input's integer word length - 1) bit before processing it in the loop. Anyway, it's also ok for your current VI if you don't care about the lost LSBs of the input.
Besides, could you tell me why you use a signed type for the Input (I20.4 in your VI)? Since zero and negative values cannot produce a reasonable result in FXP Natural Logarithm, I think an unsigned input might be better to avoid some undefined results.
Please let me know if anything else I can help.
-Ellen
帖子被Ellens在
04-30-2008 04:51 AM时编辑过了
