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# Multisim and Ultiboard

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## layer sequence

Hi there,

I need a way to indicate the layer sequence on my 4-layer PCB.

The idea is on each layer, the number of the layer should be placed.
Top layer is 1, Inner 1 = 2, Inner 2 = 3 and bottom = 4..
Now I would like it to be a little different than the image (which is how it is now). Changes:
- number 2 should be cut around the number, not a box and the number in copper. The number should be just the green PCB material.
- around number 3 and 4 shouldn't be the ground plane of layer 2 (Inner 1). With the keep out area it works, except for the DRC errors (just ignore this or?)

Orders of the manufacturer..

Message 1 of 4
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Solution
Accepted by topic author Jaip

## Re: layer sequence

Hello Jaip,

Is this still an active question?

Can you share a sample project of what you currently have? (you can remove any "not shareable" components)

If I understand correctly, then you have 4 layers?

1 = Copper Top

2 = Copper Inner 1

3 = Copper Inner 2

4 = Copper Bottom

Based on the explanation it is not a 100% clear how it should look.

2) the copper should go up to the border of the keep out area in that region you want to have a "2" cut out.

So this would come down to creating a keep out area (that is the number 2) in a copper plane, right?

3 and 4) this can indeed give DRC errors.
What does the error message say?

If I'm understanding this in an incorrect fashion, then please let me know.

Kind Regards,
Thierry C - CLA, CTA - Senior R&D Engineer (Former Support Engineer) - National Instruments
If someone helped you, let them know. Mark as solved and/or give a kudo. 😉
Message 2 of 4
(5,286 Views)

## Re: layer sequence

Hello ThiCop,

I'm very sorry for not responding! It's wasn't my intention to be disrespectfull!

Because off the fact that I found a solution (or a way around 🙂 ) and had allot on my mind, I forgot te reply!

Kind Regards, Belgium student

Message 3 of 4
(5,211 Views)

## Re: layer sequence

Hello jaip,

That is not a problem at all.

Due to teaching courses I have also been the majority of my time out of office.

Therefore there are also quite some delays in my forum responses.

Good luck with the upcoming exams!

Kind Regards,
Thierry C - CLA, CTA - Senior R&D Engineer (Former Support Engineer) - National Instruments
If someone helped you, let them know. Mark as solved and/or give a kudo. 😉
Message 4 of 4
(5,180 Views)