Hello scorpsjl,
Let me see if I can address your questions.
Is there always an error thrown when the card skips over / misses samples?
With a hardware-timed operation using a sample clock, the device will acquire/generate one sample per sample clock. The only way something will be skipped or missed is if the buffer becomes full before your program can read in all samples. If this happens, you will get a buffer overflow error. With a generation, if you are operating in a mode where the data in the buffer cannot be regenerated, you will get a buffer underflow error if you try to write a sample before the buffer has been filled by your program.
Specifically, I want my AO channel operating at about 44 khz (44,000 samples / second), and want my 16 AI channels sampling at around 10,000 samples a second (10 khz). How can I manage this?
The AI and AO sample clock are both derived from the same master timebase on the device. You can start both tasks using a start trigger so that they start simultaneously and then the respective rates will be derived from that master timebase.
Is there some way to set up an internal clock running at a least common multiple of the two frequencies, and then have each task sample after a certain number of ticks of this clock?
You could do this using counters. They would need to be setup for a pulse generation task and after so many ticks of the source, a pulse would be generated that would be used as the sample clock for AI or AO. You would need a minimum of two counters to do this and they would use the same source. This is basically the same idea of starting the AI and AO at the same time since the same master timebase is used.
Alternatively, since my AI frequency doesn't have to be exactly 10 khz (e.g. it could be 11 khz), I could set the AO frequency to 44khz and then use its sample clock for the AI. However, I would still need to make the AI operate at only every 4 beats of sample clock. Is there a way to do this?
Yes, you would use the AO sample clock as a source for a counter and setup a pulse generation task that outputs a pulse every 4 ticks of the source.
Also, I'm curious as to the exact mechanisms at work. THe sample clock i know is a hardware mechanism. Presumably at each tick of the clock, one input and one output sample is acquired or output, via an ADC or DAC respectively. Then what happens? How are buffers involved, how is the operating system involved, and might this slow things down? In particular, since I'm assuming not everything can happen "at once" at each beat, in what order do these things happen?
The samples are transferred through the onboard FIFO and then into the PC buffer. The samples are pulled from the PC buffer into your application when you call a DAQmx Read function. This process is system dependent, but at your rates I do not foresee any problems. I don’t really understand your question about what order things happen.
As for the multiplexing and inter-channel delay, as I've said, I plan to sample around 10kS/s * 16 channels. I'll look at the knowledge base page you've cited, but for now, can you tell me around what I should expect for interchannel delay? Again, my card is M-series 6259, pci-express.
6.25 microseconds. For slower rates, the interchannel delay for this device is 11 microseconds (1 for the device + 10 that the driver adds). Once you have more channels than that convert rate can support, the convert clock rate becomes the sample rate * number of channels, which is the range you are in.
