Can't find Application Note 011, "DMA Fundamental on Various PC Platforms" on the NI website.
Can someone please send me the link?
What I'm trying to figure out is what is the packet size (chunk size) for DMA transfers on NI M series boards?
i.e. how many samples are collected into the boards FIFO buffer before
DMA transfer takes place. (How many samples (or bytes) are
transferred at a time?)
Is this packet size (chunk size) configurable? If so , what is minimum value that it can take on?
