Understanding "Settling Time for Multichannel Measurements" figures in specification doc

[ft_06]

Hello,

We have a PCIe 6353 card. In X-series manual, it is explained:

• for convert clock: the driver chooses the fastest conversion rate possible [...] and adds 10us of padding [...] to allow for adequate settling time => I guess I should play with the card setting a low sampling rate and 3 measurements to see which value the driver chooses (and substract the 10us of settling time)
• If the AI sample clock rate is too fast [...], it chooses the conversion rate so that the AI convert clock pulses are evenly spaced
• carefully choose scanning order, you should not switch from large range to small range (and generally you do not need extra settling time when switching from small range to large range)
• a technique to improve settling time is to connect an input channel to ground and insert it in the scan list (or use the internal ground)

In the PCIe-6353 spec doc, the "settling time for multichannel measurements" section gives time to reach 60ppm of step or 15ppm for a certain voltage range (10V, 5V, 2V, 1V or 0.5V or 0.2V, 0.1V) as shown in attached screenshot,for example 2us for 15ppm of step at 0.5V.

However, there is nothing on acquisition time

We would like to make the most of the card (like 100KHz sampling thus allowing max 10 channel measurements) so how should we understand these constraints ?

• if in the same range, do we have the settling time ? for example, if going from 10V to 1V configuration, 1.5us settling time is needed ? If going from 0.2V to 0.1V, is 8us required ? or is it a settling time just for going from one range to the given range ?
• or is it a max boundary and all various transitions are quite lower but this is too much work to give them all ?
• how to take into account acquisition time ? Here is an example:
  • let's imagine convert clock is 1MHz so 1 acq every us and the "15ppm of step" settling time is 1.5us
  • at t0: acquisition of channel A (next channel will change voltage range thus 1.5us settling time is needed)
  • at t0 + 1us: acquire internal ground => it gives 1us for settling time
  • at t0 + 2us: acquire internal ground => we have now 2us for settling time
  • at t0 + 3us: resume "normal" acquisition on channel B
  • could I have resumed "normal" acquisition at t0 + 2us, expecting acquisition to last less than 0.5us and settling to occupy the remaining time + 1us at t0 + 1us ? 

[ft_06]

I played with the PCIe-6353 (1MHz max multichannel acquisition rate) and "the driver chooses the fastest conversion rate possible [...] and adds 10us of padding [...] " translated correctly, for a low sampling clock of 1kHz, to a convert clock period of 11us (1us of fastest conversion rate + 10us)

Still need to understand the details of settling time constraints 😉