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USB-6341 X-Series DAQ max clock speed query

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I am using the subject line DAQ unit to generate a counter at 12.5MHz (the max supported 'External base clock frequency' of 25MHz/2 according to the spec document).

I then use the counter as a clock and detect an incoming rising edge as a trigger for a separate variably delayed output pulse.

All works ok apart from as this is a 12.5MHz clock with an asynchronous trigger I can have up to 1/12.5M jitter (i.e. 80nS clk resolution), which seems about right. 

This is borderline ok for my application, but I noted that the spec doc for the box says 'Internal base clocks' of 100MHz are possible.

 

https://www.ni.com/docs/en-US/bundle/usb-6341-specs/page/specs.html

 

Also I rooted through the DAQ X Series User manual and found that 'The 100 MHz Timebase can be used as the timebase for all internal subsystems. The 100 MHz Timebase is generated from the following sources: Onboard oscillator'.

 

So can this 100MHz clock (probably usable would be 100MHz/2) be used as my base clock for trigger detection? or no it cant because the function I need to use isn't classed as an 'internal subsystem'? I am using LabVIEW 2021 but I guess this is a more generic question about the performance of the box hardware and clarifying the spec nomenclature.

 

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Solution
Accepted by topic author MrSpanman

Summary: yes, you can use the 100 MHz internal timebase to get your timing quantization down to 10 nanosec.

 

I wouldn't use the term trigger "detection" b/c that kinda sorta implies something like sampling and comparison at a rate governed by the timebase.  It's not really like that.  It's logic circuitry that *reacts* to a trigger edge in hardware.

 

For the most part, the 100 MHz timebase will be used by default for counter measurements and pulse generation.  And that's a full 100 MHz, you don't need to divide by 2.   So you can get your jitter down to something like 10 nanosec instead of 80.

 

(For anyone wondering what "jitter" I'm talking about: because the trigger activates the hardware logic circuitry directly, it isn't synced in any way to the 100 MHz clock.  So the triggering edge can happen at any phase within that 100 MHz clock cycle.  The counter measurement or pulse generation will be driven by and synced to the 100 MHz clock however, so there will be jitter in the time between the trigger and the active edge of the timebase.)

 

 

-Kevin P

CAUTION! New LabVIEW adopters -- it's too late for me, but you *can* save yourself. The new subscription policy for LabVIEW puts NI's hand in your wallet for the rest of your working life. Are you sure you're *that* dedicated to LabVIEW? (Summary of my reasons in this post, part of a voluminous thread of mostly complaints starting here).
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