03-26-2014 08:37 AM
I have a data acquisition system which consists of a PCIe-6321 X series card and a 9636 sbRIO. I mostly use the sbRIO for high accuracy counter tasks, but I also use it to produce a 50% duty cycle timing clock for a set of sample and hold amplifiers, measuring three differential pairs. The outputs of these amplifiers are measured differentially on the 6321. I’m trying to correct my analogue input measurements for the output bias of the S&H amplifiers. With a reference voltage source connected to each leg, the differentially received voltage should be equal to 0 V.
I wrote a little test VI to record 20 s of data on the three differential channels and dump it into a TDMS file. Leaving the timing source as the default sample clock (see simple block diagram for one diff pair) I saw my expected noise of the order of the LSB with a low frequency component superimposed. The frequency of the low frequency steps is approximately 0.4 Hz. As I’m receiving differentially, it’s not common mode noise that causes that step. Furthermore, I’d expect it to be broadly in phase – yes, I know it’s not a simultaneous acquisition device, hence the S&H buffers and the external clock, but I wouldn’t expect a delay of 0.25 s or so between three channels at 50 kHz.
Fortunately, for sync purposes I usually time the PCIe DAQ via the same external clock signal produced by the sbRIO and wired to a PFI line on the PCIe card. Changing the timing source of the VI to the rising edge of this PFI line, the low frequency step disappears.
Other than the DAQ timing source, there is no difference between the two tests.
Any idea what could cause that low frequency superimposed signal in the first plot?
03-26-2014 01:27 PM
My guess would be a beat note between the two 50 kHz oscillators. If this is the situation, repeating the test several times (with the equipment remaining powered on) at intervals of a few minutes will probably show a phase shift (or even a frequency change) on the low frequency signal.
Lynn