Ian,
I am going to guess that you are experiencing this problem because our S-Series boards such as your 6120 use a pipelined FIFO ADC process. Specifically, our S-Series boards do not send the last 3 samples of an acquisition when using an external clock. The last three samples remain in the FIFO on the card. Therefore, if you begin your acquisition, receive a trigger pulse, then receive 9,984 clock edges on the sample clock, and then read all the samples in the buffer, you will only receive 9,981 samples. Consequently, if you set the AI Read.vi to read 9,984 samples it may timeout because it is still waiting for three more samples to be acquired. This would create the allusion that the external clock was not working with the 6120.
The good news is that i
t is easy to solve this issue. You simple need to read 3 less samples the first time AI Read is called. Therefore, the first time you call AI Read you need to read 9,981 samples and then the next time you call AI Read you will continue to read 9,984 samples. This will ensure that you will get the same number of samples between triggers except for the first time which will be short three samples. However, with this method, the first three sample of each trigger will be the last three samples from the previous trigger signal.
Please see this KB for additional information on how to ensure that you get the proper amount of data for each trigger signal that you receive:
http://digital.ni.com/public.nsf/websearch/D64CD277A6B739A186256A73007E7BCC?OpenDocument
Please let me know if you are still having difficulty or if the information I provided did not help resolve the issue.
Regards,
Bill B
Applications Engineer
National Instruments