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vi running bit

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Hi

Is  there a funciton that can show the vi status is running or not?i wang pass this bit to PLC

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Hi pi number,

 

Is  there a funciton that can show the vi status is running or not?i wang pass this bit to PLC

Do you want to test the execution state of the very same VI which runs that test? Then the result will always be the same!

 

You can test the execution state of other VIs using a property node of the VI class name "Execution.State"…

Best regards,
GerdW


using LV2016/2019/2021 on Win10/11+cRIO, TestStand2016/2019
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Hi 

I use OPC to transfer this running bit,i want to know the Main status,but if the main VI stopped the OPC bit still stay "True"

If the Main VI stopped but the OPC should still working it will scan the interface and can see there is no signal coming from LV,but actualy the running bit status did not chagned after the Main VI stopped,How come?

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Hi pi,

 

how do you transfer that information?

Why don't you switch off this "bit" before you exit the "Main VI"?

Best regards,
GerdW


using LV2016/2019/2021 on Win10/11+cRIO, TestStand2016/2019
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Solution
Accepted by topic author 314159ym

You might want to use a watchdog. Let the VI toggle a Boolean, for instance at 2 Hz. The PLC will then detect the changes, and know the VI stopped when there is no change for .6 sec.

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Hi 

 

Good point,will test this

Thanks

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HI

Is this watchdog has to under the FPGA?My project is not running under FPGA,and how to generate the 2HZ signal?

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@314159ym wrote:

HI

Is this watchdog has to under the FPGA?My project is not running under FPGA,and how to generate the 2HZ signal?


It doesn't have to be.  You just need a Boolean to toggle every so often, preferably in your main loop.


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@314159ym wrote:

HI

Is this watchdog has to under the FPGA?My project is not running under FPGA,and how to generate the 2HZ signal?


You could even have 2 watchdogs, one for the FPGA, one for the PC code. With as side note that if the FPGA stops working, you might get a PC failure for free.

 

This is really up to you. If the FPGA has the critical code, putting the watchdog it's main loop might make sense. If the PC does critical things, putting it there might be better.

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