timing violations loop name doesn't exist...

[paubine]

This loop L73998316 is not in my code... I have this error since I added FPGA PID (fpga 8.6)..

any ideas?

Thanks

Patrick

Status: Compilation failed due to timing violations.

The compile process reported timing violations in the following Timed Loops:
  * L73998316, using clock 40 MHz Onboard Clock

Suggestions for eliminating the problem:
  * For Timed Loops with timing violations
      - Reduce long arithmetic/combinatorial paths
      - Use pipelining within Timed Loops
      - Reduce the number of nested case structures
  * Reduce clock rates if possible
  * Reduce the amount of application logic to make routing easier
  * Recompile

Refer to the LabVIEW Help for more information about resolving compilation errors. Click the Help button to display the LabVIEW Help.

Compilation Summary
-------------------

[Hillman]

HI Patrick,

Thanks for the reply and I hope your well today.

This error has been seen a few times before, however I am interested in your case as you appear not to have loop with that name, is that the case? 

If you remove the FPGA PID - you dont see this error?

Pipelining has resolved several cases of this error in the past, pipeliningto optimize FPGA VIs link here - explains a bit more.

http://zone.ni.com/reference/en-XX/help/371599D-01/lvfpgaconcepts/fpga_pipelining/

Do you have any other timed loops - could it be possible that the name is just wrong?

[paubine]

Hi James, 

I also had this error before and I solve the problem with pipelining and sometimes, just by recompiling make it worked (the achieved rate was really near the requested rate)...

But this time... since I added the FPGA 8.6 PID I have this error (name of timed loop timing violation). (35Mhz achieved vs 40MHz requested) but I do not find this timed loop name in my code...

Andrew from NI is working with me on this error ...

Andrew and I opened the FPGA 8.6 PID and there is 2 Timed Loop in the express VI, I'm currently trying to recompile with a 32 MHz clock do see if it will solve the problem...

Thanks for your help,

Patrick

[paubine]

The compilation went successfully by changing the two Timed Loop inside the FPGA PID express VI to 32 MHz instead of 40MHz...

[Hillman]

Hi Patrick,

Good Morning and I hope your well.

Is this an Andrew from the UK Office?

I am glad you've managed to resolve this.. but does this mean you can't get your requested rate?

There does seem to be a CAR on this express VI for LabVIEW FPGA 8.5, so if you could either tell andrew or provide some more details of what the issue was I can submit one for LabVIEW 8.6, 

Thanks,

[paubine]

I don't know which Andrew I talk to... (application engineer FPGA when i call to the 1800...)

As for the 8.6 FPGA PID express VI... I can't compile it, even alone in a fpga code... try it ...

Pat