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time delay feedback

Hi Steve,

 

I hope your well today.

 

I was wondering if you got the example code working and what your thoughts were?

Kind Regards
James Hillman
Applications Engineer 2008 to 2009 National Instruments UK & Ireland
Loughborough University UK - 2006 to 2011
Remember Kudos those who help! 😉
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Message 11 of 24
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Ben wrote:

Yes, but the extent of that capability is limited by the OS you run under as well as the CPU,  channel count, and sample rate.

 

In Windows you can set up continuouse double buffered acq from th AI and just write that buffer to the output. In this scenario you are going to get your data in big piles so the size of the pile will limit how quickly you can apply a change to the phase delay.

 

If running in RT, and your update rate is less than 30 kHz, single channel, and using top of the line CPU then the time delay between requesting a phase change is limited by the comm method you are using to submit the change to the phase. If you use another AI channel to control the phase, then the change can be realized within one update.

 

If you switch to an FPGA solution, you could apply the same idea and run as fast as 40 MHz.

 

Ben


BTW,

FPGA could generate AO waveforms at 1us resolution.  Could read AI and delay to AO with a resolution of 1.3 us on latest hardware.  5 us on older RIO hardware.  only digital goes 40 MHz.

Stu
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Message 12 of 24
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Thanks for all the help people,

 

If I change the second waveform generator to a store array, can I then store the data that the first AI reads from the experiment as a waveform and then send this to the AO to generate this stored waveform (with controlled time delay)? A time resolution of ~2-3us on this delay would be good.

 

Steve

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Message 13 of 24
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Hi Steve,

 

Thanks for the update and I hope your well today.

 

I am afraid you won't get a resolution in the us on the windows machine which I wrote that code for. You would require a real time operating system. The best windows could provide would be a via ms.. with efficent code. 

 

You certainly could store the acquire waveform to output at a later date. One method could be to store it in a FIFO/queue or save the data to a file. However, I think both of these would take some time. 

 

Please let me know if you are using Real Time and how you get on with your code, 

Kind Regards
James Hillman
Applications Engineer 2008 to 2009 National Instruments UK & Ireland
Loughborough University UK - 2006 to 2011
Remember Kudos those who help! 😉
Message 14 of 24
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Does NI supply any hardware options for what I would need? Just for clarification, I have supplied a schematic diagram of what I need.

 

Cheers,

 

Steve

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Message 15 of 24
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Hi Steve,

 

Thanks for the reply and the kudos. Many thanks.

 

I'd say any RealTime/FPGA based application could achieve this. Such as the cRIO or an FPGA PCI card running on an RT PC. 

 

The real time OS runs in the us range and significantly less jitter than a windows machine.  I'd say the FPGA memory would be ideal to store and then generate a waveform from. 

 

For example you could continuously write to memory (FIFO/BUFFER) and read from the memory, with a delay in the FPGA code. By just wiring the AI data points into a FIFO (buffer) and then with a time delay between the the start of the AI acquire and the AO output - the AO could just output AI samples.

 

But FPGA/RT costs more than the standard labview/DAQ application on a windows machine. I'd recommend you contact your local sales office - you can find this information from ni.com and ask to speak to your internal sales representative. They could book you a meeting with your local Field Engineer - who'd be more than happy to visit you and discuss your applications and your experience so far with NI. 

 

I hope this helps, 

Best wishes,

Kind Regards
James Hillman
Applications Engineer 2008 to 2009 National Instruments UK & Ireland
Loughborough University UK - 2006 to 2011
Remember Kudos those who help! 😉
Message 16 of 24
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bobdone wrote:

Does NI supply any hardware options for what I would need? Just for clarification, I have supplied a schematic diagram of what I need.

 

Cheers,

 

Steve


 

Is your schematic imply summing the two AO channels?

Are you outputing the AO reference, acquiring AI, delay AI and add to AO reference for new output?

If this is to be performed in real time, the PCI-785X series FPGA card is the one to use.  I will post an example of what I think you need soon.  the cRIO FPGA hardware is too slow for this app.

Stu
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Message 17 of 24
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stu@viewpointusa.com wrote:

bobdone wrote:

Does NI supply any hardware options for what I would need? Just for clarification, I have supplied a schematic diagram of what I need.

 

Cheers,

 

Steve


 

Is your schematic imply summing the two AO channels?

Are you outputing the AO reference, acquiring AI, delay AI and add to AO reference for new output?

If this is to be performed in real time, the PCI-785X series FPGA card is the one to use.  I will post an example of what I think you need soon.  the cRIO FPGA hardware is too slow for this app.


attached example shows FPGA AI to AO.  fastest way to do what you described.

Stu

Stu
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Message 18 of 24
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Hi Stu 

 

I'm not summing the two AOs. I have two seperate inputs to my experiment for the AOs. So basically both AOs are running at the same time outputting different waveforms. The first AO is generating the original sine wave. The second AO waits for the waveform to be aquired from the first AI and then shifts this waveform in time (on the scale of us) and the second AO then generates and outputs this waveform. The second AI reads in and saves the data to file.

 

Can the FPGA card you spoke of still carry this out?

 

Cheers,

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Message 19 of 24
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Hi Steve,

 

 Thanks for the reply and update.


Stu is right, the FPGA PCI card range would be a good solution for you if your deploying application in the Lab. One of the major benefits with the cRIO is its size and robustness. 

 

The FPGA PCI cards do have a better performance. You could certainly perform the DAQ application which you've mentioned with the us resolution using the PCI Cards.. you just have to code it efficiency and effectively. Do you have much experience with FPGA programming?

 

Thanks, 

Kind Regards
James Hillman
Applications Engineer 2008 to 2009 National Instruments UK & Ireland
Loughborough University UK - 2006 to 2011
Remember Kudos those who help! 😉
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Message 20 of 24
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