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set sample rate for FPGA

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Hi,

 

Now I'm testing the NI-9220.And the maximum sample rate is 100kS/s/ch, 10us, but I can't not achive it at the same time. First I creat FIFO(named AI(Testing)), then FPGA VI and Project VI.

 

Attach file is my testing VI. Please ignore some discrepancy. And "Project VI" is always this structure. 

 

1. When I test one port, such as AI0, I use "FPGA VI" and "Projec VI"(use for one port), with configuration 10us(sample rate, input control), I get the result of 20us(Actual sample rate, using 1khz square wave, I count the number of the picture).Howerver, 1us gets the result of 10us. I re-arrange the possibility of "FPGA VI", sometimes, I get 10us of result 10us(correct).

 

2. But when I test two port, such as AI0 and AI1, I use "FPGA VI with two port" (just the same structure), with input 10us, I get the result of 20us. Then I test 16 port with input 10us, I get the result of 160us. Then I guess, with this structure, when testing N port, I get the actual sample rate of N*10us which is limited by the FIFO number(I just use one FIFO named AI(Testing)).

 

3.Then I use two FIFO, with structure "FPGA VI with two port " for testing two port, AI0, AI1. Then I still get the result of 20us (input 10us). 

 

So what's wrong in my VI? How can I get the true result? That's mean when I input 10us, my actual sample rate is 10us rather than 20us...etc

 

And the up structure means that I use the same idea to creat the VI for N port.

 

Thanks

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Hi mhsj,

 


@mhsj wrote:

Attach file is my testing VI. Please ignore some discrepancy. And "Project VI" is always this structure. 


There are no VIs and no project file. You just attach some images: we cannot debug/edit/run images in LabVIEW!

Next time please attach a ZIP file containing all the files of your project, including the lvproj file!

 


@mhsj wrote:

So what's wrong in my VI? How can I get the true result? That's mean when I input 10us, my actual sample rate is 10us rather than 20us...etc


There is so much wrong…

  • What's the point of having a FOR loop iterate just once?
  • Why do you need two FOR loops to read two AI channels?
  • Why do you need two wait functions to set a samplerate in just one (while) loop?
  • Most significant: when you want to read two channels from the very same module you should use only ONE (1) IO node! You can change their size to access several channels!
  • When you want to read at the max rate of your AI module then you probably need no wait function in the loop, the IO node will wait for the next sample (from my experience with other modules, but check/verify that with your module)…

When you would have attached real code I would have made some edits to show all this to you…

Best regards,
GerdW


using LV2016/2019/2020 on Win8.1/10+cRIO
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sorry for late with the project file...I'm not familiar with it.

 

1.One cycle time of FOR loop is a remaining term, last time I use 50 point. Then I find 50 point is not convenient for caculating the setting sample rate. So I use one instead. For one port, I think it has no influent on 9220.

 

2. Someone tells me that use one FPGA/IO for N port, such as, AI0, AI1, the lower one may drag the fast one, which means that I have to read data before the lower port accomlished. So I use two FOR loop and two IO node.Maybe I need two while as well.

 

3.To get the max rate of the AI module, I set the input with 0us, but I still get the lower rate using last structure.

 

4.According to your addvice, I fix the VIs, and zip it. Can you give more addvice on it?

I want to have a difference sample rate on 16 AI port if I need, and they can get the maximum as well. So I  use the familiar structure using you addvice.

 

Thanks

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Your main problem, as Gerd already pointed out, is that if you want to read more than one channel from a module simultaneously you MUST read them with the same IO node. Currently each IO node in your diagram will initiate a sampling cycle and return its value for the required channel but they can't execute in parallel since they use the same IO resource. By specifying all the channels you want in the same IO Read Node, the FPGA compiler can synchronize them properly and return all requested IO channels in the same cycle.

 

And while the module will indeed limit the IO Read property to its maximum sampling speed, it may still be a good idea to use a fixed timing on the diagram, but I prefer to do that with a Single Cycle Timed Loop.

 

What you heard is probably something else. If you combine multiple channels from different modules in the same IO node, the channel from the slowest module in that node will determine the timing of the IO node. So including a channel from a thermocouple module for instance in the same IO Node as your 9220 channels, will limit the reading speed to the maximum speed of the thermocouple channel, which depending on the module is usually around 5 to 100 samples per second.

 

But separating them into their own IO Nodes and adding them into a seperate loop that executes only once is still not enough if they are then included in another loop. That loop has to wait until all the code inside has executed meaning the slow channel still determines the loop speed.

 

You can totally forget that 1 iteration loop in your diagram, it serves no purpose at all! If you need to sample two modules with different speed you have to put them into totally independent loops!

Rolf Kalbermatter
Averna BV
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Thank you for your advice. I tried agian for a day and find a new problem...

 

1. I use one IO node to read the data and test the running time of the while loop, it's 134us(with input time interval 10us). So in this case, I can't understand, in FPGA vi, every time I accomplished the loop with 134us, I can get a sample rate of 10us or below it(use 1kHz squared wave, I count up to 100 points).

 

2. So the 1 tells me that reading from IO node and write to FIFO needs 134us. The Sequential Structure and Timer can not achieve max sample rate. Then I think about a Single Cycle Timed Loop. Howerver, 9220 node can not put into it, and, unless Single Cycle Timed Loop stops, the data flow can't no get out of it. Then I use a Local Variable, after testing, I find the swtiching speeds of Local Variable can't keep up with the speed.

 

So I think it's a littile conflict(I can't not use data flow of a Single Cycle Timed Loop and Local Variable). And I don't find any "Switching controls" in labview, I get confused now, Can anyone offer some advice, especially for Single Cycle Timed Loop ?

 

Attached file is my testing project, thanks.

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Solution
Accepted by topic author mhsj

For your FPGA one port.vi:

 

Do not use the Wait-VI, if you want to achieve a given sample rate; Use the Loop-Timer:

JensG69_0-1633697895962.png

Otherwise the timing needed for the FPGA I/O node, the Write-FIFO and the while loop (that will be two additional ticks) will be added on top of your wait vi.

 

For two channels, just expand this one-port vi (but again with the loop-timer !!! And exactly like this, inside a flat sequence) to reading two AI from one FPGA I/O node.

 

Regards, Jens

 

P.S.: Search for 9220 in the NI example finder, you can find several FPGA-examples for that module.

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