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We appreciate your patience as we improve our online experience.
06-14-2016 09:12 PM
The data coming out of the DMA FIFO is being rounded and I can't figure out why. The vi's shown here are simply sending an array into the FPGA from the host and then back to the host. When it arrives back at the host the data has been rounded down. I'm assuming some truncation is happening? Anyone have any idea how I can fix this? I'm new to this so any suggestions would be very much appreciated.
06-14-2016 10:24 PM
What is the datatype for your FIFO?
My guess is that it is an integer. See if you can define another datatype to it. Though you should try to stick with integers or fixed point numbers on an FPGA. They take up a lot fewer resources on an FPGA than floating point numbers.
06-14-2016 10:47 PM
The data type is an I16.
So do you suggest that I convert all these decimals into integers by multiplying by a large number going in and divide by the same number coming out? Or is there a better method?
06-14-2016 10:49 PM
06-14-2016 10:54 PM
06-14-2016 10:57 PM
Yes, I realize now that the integer type is the problem.
I won't just be transfering numbers around. I was just learning how to use the DMA FIFO. I'll be doing some matrix multiplication and some other basic math functions. Do you still recommend I keep using floating point numbers for that and only switch when I hit performance limitations or run out of space?
06-14-2016 10:57 PM
Found it. Thank you.
06-14-2016 11:04 PM