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real-time system with simulation interface toolkit

Jarrod,

Thank you very much for your help!
Obviously, RTX is not a very good choice for my application. I will try to figure out whether I can use ETS and hope it works.

Yves


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Message 11 of 18
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Hello,



I hope this fits a bit under this subject. I’m using SIT to run a simulink model on a Crio 9022 controller. This works good, until I try to decrease the fixed step in simulink below 0.001 seconds (1kHz). I need a sampling of more than 1kHz, but if I try to run with for example 5kHz, the Crio gives the next error.

 

Error 14120 occurred at Driver VI >> testtttt_Driver.vi >> testtttt_Base Rate Loop.vi >> NI_SIT_driversupportVIs.lvlib:SIT Take Model Time Step.vi:

 

Possible reason(s):

 

Simulation Interface Toolkit:  The base rate loop did not finish in time.  The combined time of computing the model and performing input and output is too long. Increase the model time step, switch to a simpler solver, or reduce the number of inputs and outputs used.

 

I tried already with really easy simulink models (with input/output), with easy solvers and he still generates this error. So the reasons suggested by the error message are probably not an option.

What should I do to solve this, or is this just a limitation of the SIT. Do I maybe have to change something in the FPGA bitfile? My input module is the NI 9201 and the output module NI 9263.

 

Thanks a lot,

Sam Weckx

 

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Message 12 of 18
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Howdy Sam,

 

It seems that there could be a few issues that might be slowing down your loop rate here.  The 9022 should be capable of much higher frequencies, so I don't believe it's a hardware limitation.  Also, SIT can operate much faster than 1 kHz, so I'm not sure the limitation is there either.  The 2 places I see a potential problem are in the FPGA bit file (like you mentioned) and the number of input/outputs that you have.  Did you develop your own bit file for the FPGA, or are you using LabVIEW to do this?  The issue might be in getting the signal through the FPGA.  

 

Additionally, I'd like you to run a simple 1 input 1 output simulation with very little complexity and see what happens.  Can you post a copy of your model and the code that you're using?  I'd be curious if anyone else has seen this issue.  

 

Thanks, I look forward to hearing back!

Sincerely,

Chris G in AE
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Message 13 of 18
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I did develop my own fpga bit file for the FPGA using Labview ( I did it like in the link: creating a custom fpga bitfile, http://zone.ni.com/reference/en-XX/help/371504D-01/lvsithowto/sit_h_custfpga/ ) I use the chassis 9113. I did nothing change in the grey time loop like they say, I only removed the modules and added the ones i use and compiled afterwards.

My normal model is quite big, but I also tested with another easy one (one input, one output). I added that simulink model, my vi and my fpga bitfile to this post.

 

Thanks a lot for your help,

Sam

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Message 14 of 18
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is there any solution about this problem.

 

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Message 15 of 18
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Hello Sinan,

 

It sounds like you are having issues with timing/loop rates when using the Simulation Interface Toolkit, but there are a few issues mentioned in the previous posts- could you be a bit more specific about what problem you are currently looking for a solution for?  Is your simulation running on a nondeterministic desktop machine, a RIO, or Real-Time PXI?  What software or development platform are you using? Are you seeing any errors, or is the system running slower or faster than anticipated?

 

Additionally, as it has been over five years since the thread was created, it is unlikely that the original posters will see or respond to your question; you may have better luck creating a new thread with a problem description specific to your application and the behavior you are currently seeing to encourage new forum responses.

 

Regards,

Tom L.
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Message 16 of 18
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Hello Tom;

 

my harware's are:

NI cRIO 9025

chasis cRIO 9112

Analog input NI 9215

Analog output NI 9264

 

the example sinwave problem matlab model is 0.005 fixed step size.(0.2 kHz)

 

i change the step size to the 0.00005 fixed step size (5E-5) (20 kHz)

 

then it gives the error 14120 it is in the attachments picture.

 

how can I work cRIO 9025 and SIT with higer step size 20 kHz or more.

is there any trick to crate custom bitfile releted to timing.

 

Regars.

Sinan Başaran - GYTE

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Message 17 of 18
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Hello Sinan,

 

It looks like you are also working on an issue via this thread:

 

SIT cRIO 9025

http://forums.ni.com/t5/Real-Time-Measurement-and/SIT-cRIO-9025/td-p/2122360

 

in addition, there is also an NI branch assisting you at this time- is this the same problem?  Based on the screenshots and information you have provided, I agree with Alisha that this appears to be a limitation of the model and/or controller's resources.  By increasing the number of steps by 100-fold, it is likely that you have drastically increased the amount of RAM and/or CPU time required to run the model- it is quite possible that a single 800 MHz processor cannot run your model at 20KHz.  I would recommend installing the system state publisher service on your 9025 and monitoring memory and CPU usage via the Distributed System Manager to ensure that the system isn't maxing out.  The following document describes how to use this tool to investigate your system's resource utilization after installing the System State Publisher via Measurement & Automation Explorer:

 

Monitor NI CompactRIO System Resources and I/O with the Distributed System Manager

http://www.ni.com/gettingstarted/setuphardware/compactrio/systemmanager.htm

 

Regards,

 

Tom L.
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Message 18 of 18
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