"Unlocking" C 9401 30 MHz sample rate

[JScherer]

Per the data sheet and and this question , I understand the NI 9401 max 2 channel read speed is 30MHz.

You can sample the 9401 at a 25ns rate as the 100ns spec is the propagation delay from the input pin to when you would read it on the FPGA.  The specs from the 9401 manual are below.

Propagation delay
Input ........................................... 100 ns max
Output......................................... 100 ns max

Maximum input-signal switching frequency by number of input
channels
8 input channels..........................9 MHz
4 input channels..........................16 MHz
2 input channels..........................30 MHz

I understand that the 100ns propagation delay means the FPGA will be lagging but I'm alright with that delay. How do I configure my FPGA (NI 9306s and 9309s) to read a 9401 card at this higher speed? Is it enough to just put the reading node into an SSTL?