Highest read speed possible with NI9401

[Gryphon]

Hi All,

 I have a project in which I would like to read 8 - 24 digital input lines to detect changes on each line from low to high. I would like to do so in such a way that I will have a resolution of 25 nanoseconds or better on when a particular line transitions from low to high.

 I have tested the NI 9401 in a compact DAQ chasis and have been able to read the DI at a frequency of 20MHz.  The device does not allow a sample clock rate higher than 20MHz on the compactDAQ or a time base higher than 20MHz.  Using the 20MHz sampling, I can detect changes with a time resolution of 50 nano seconds which is pretty good.

 My question is whether I would be able to do better with a compact RIO setup.  I have read that the IO can be read at up to 40MHz.  Does this mean that I can then achieve 25 nanosecond resolution with digital IO using the 9401 on a compact RIO chasis or am I limited to the 9401's specified 100nano second resolution.

 If the 9401 was trully limited to 100 nanosecond resolution, surely I would not have been able to consistently read with 50 nano second resolution a digital signal with a high time of 50 nanoseconds and a low time of 50 nanoseconds.  Also when the 9401 is used on slot 5 of the compactDAQ which allows the use of the counters, it can generate pulses (granted they aren't beautiful squares) down to 25 nano seconds high and low periods.

 So what do you think?  Am I trying to do the impossible or can I get super fast, reliable DI reading with the compactRIO.

Thanks for reading,

Peter

[Ima U]

Hi Peter,

The CompactRIO chassis does have a faster clock than the CompactDAQ chassis due to the FPGA. However, you are limited by the propagation(I/O) delay of the C Series Modules. The I/O delay time for the 9401 is specified for 100ns. The 9401 may or may not work outside of specification but you are not guaranteed a clean signal.

If you are looking for a faster I/O delay time you should consider an R Series module with the CompactRIO chassis programmed with LabVIEW FPGA. I hope this helps.

[Bassett_Hound]

Hi Peter,

You can sample the 9401 at a 25ns rate as the 100ns spec is the propagation delay from the input pin to when you would read it on the FPGA.  The specs from the 9401 manual are below.

Propagation delay
Input ........................................... 100 ns max
Output......................................... 100 ns max

Maximum input-signal switching frequency by number of input
channels
8 input channels..........................9 MHz
4 input channels..........................16 MHz
2 input channels..........................30 MHz
Maximum switching frequency by number of output channels,
with 1 mA, 50 pF load
8 output channels........................5 MHz
4 output channels........................10 MHz
2 output channels........................20 MHz

As you can see its really the switching frequency that you have to be concerned with, which does allow you to input and read signals at the rates you mentioned in the post above.

Steve

Message Edited by Bassett Hound on 08-23-2007 12:15 PM

Message Edited by Bassett Hound on 08-23-2007 12:16 PM

[Gryphon]

Hello Ima, Steve,

 Thanks very much for your replies.   

 Ima,  thanks for pointing out the R series cards.  I had not really had a good look at them before and they would definitely do what I want except for this particular application, because it has to be battery powered and EXTREMELY rugged, it is more likely that I will have to use the compactRIO and 9401 approach.   I don't however see that there would be any use in connecting the R series to C series modules through the cRIO 9151 as the IO lines would be then subject to the same transmission delays as the FPGA in the compact RIO.  The R Series would be great to interface to customised interface circuity though and I will look at this.   

Steve, I had looked at the specs but somehow only after reading your post did it tweak in my head that the delays are probably more serious with output switching.  One really important thing you pointed out to me is the dependance on the number of channels being read from or written to which I did not expect or register earlier.

 I will have to do a little more testing on multiple channel reads at 20MHz frequency with input signals out of phase on each channel.  Going to be hard/expensive to do that on multiple channels.  I will try and post back with results when I can.

 Thanks again for your help guys!!

Cheers

Peter

[Ima U]

You are very welcome Peter. Feel free to post more questions once you have more results.