problem with memory block in labview 2009

[DDAAMMIIRR]

Hello everyone,

I got "ERROR:MapLib:979 - LUT4 symbol" during the compiling proccess (a lot of ERRORs like this one), and I discovered that the reason for my problem is MEMORY BLOCK.

To be sure that the problem is in this block, I made very simple project in LabView 2009 (on FPGA Target PCI5640R) just with usage of this block as you can see on attached picture as well as in file test_memory block.lvproj on attached link: https://www.dropbox.com/sh/u87f1oihelmm4dq/Jo_6-bICSf

I have a problem with compiling VI with this block, and I get so many ERRORs like:

ERROR:MapLib:979 - LUT4 symbol
"window/theVI/n_00000036/nSCTL_00000013_00000014/n_000000A3/cOutLoc<0>1"
(output signal=window/theVI/res000001ed_wi<2>) has input signal
"window/theVI/res0000020d_wo<1>" which will be trimmed. See Section 5 of the
Map Report File for details about why the input signal will become undriven.

or

ERROR:MapLib:978 - LUT4 symbol
"window/theVI/n_00000036/nSCTL_00000013_00000014/n_000000A3/cOutLoc<23>1"
(output signal=window/theVI/res000001ed_wi<25>) has an equation that uses
input pin I2, which no longer has a connected signal. Please ensure that all
the pins used in the equation for this LUT have signals that are not trimmed
(see Section 5 of the Map Report File for details on which signals were
trimmed).

Whole report you can see in file report.txt on attached link.

I would really appreciate if anyone could take a look on my problem with simple project and suggest me a solution.

I'm really stuck with my bigger project that need to have this memory block.

I'm looking forward to hear from you,

King Regards

ing. Damir Hamidovic

[Joel-I]

Hi DDAAMMIIRR,

Try taking a look at this thread and seeing if that addresses the issue you're seeing:

http://forums.ni.com/t5/LabVIEW/ERROR-MapLib-979-LUT4-symbol/td-p/1293328/page/2

[DDAAMMIIRR]

Hello Joel I,

Thanks for your suggestion, but I have already seen that link and neither of those solutions wasn't appropriate to me. (I don't have any CLIP nodes, so one of the sollutions with changing upper case .VHD to lower case .vhd isn't sollution for my problem. Also, I tried to change Xilinx Options in FPGA Target as someone mentioned as a sollution (I changed "Design Strategy drop-down box" to "Area", but it didn't helped me too.)

I would really appreciate if someone could take a consideration of this kind of problem !

King Regards

ing. Damir Hamidovic

[Joel-I]

Are you able to run any of our shipping examples for FPGA?

I've attached an example I've downconverted from LabVIEW 2013.  Follow the instructions and let me know if you get the same error.  

Also, to upload files, please upload it directly to the forums.  

[ThiCop]

Hello Damir,

I'm going to subscribe myself over here (instead of using private messages) so that I can keep track of the latest status of the issue.

Please post the results of your tests over here to keep track of the issues in the most optimal way.

[DDAAMMIIRR]

Hello,

I'm really sorry for my long delay, but I haven't had access to a labview and FPGA target.

Now I have full access.

First, I can run all examples (every I tried) and I can compile and modify 'code' at FPGA target in every example that doesn't contain memory block, but I cannot compile (and so,cannot make any changes in 'code' on FPGA target) any example that does contain memory block.

Second, I open project that you attached, but I cannot even open 'Memory.vi' , and so, I couldn't run project. (Memory.vi [warning:has been deleted, renamed or moved on disk] )

You can see it on picture:

Just to mention, my FPGA target is PCI-5640R

King Regards

[Matthew-B]

Hi DDAAMMIIRR,

Are you currently using target-scoped memory or VI-defined memory? Does the same thing happen if you switch to the other?

Best Regards,

[DDAAMMIIRR]

Hi Matthew,

I'm currently using target-scoped memory and I've just tried to use VI-scoped memory insted of target-scoped and I got the same ERRORs.
(you can see simple project with memory that I cannot compile and report that I got in attachement)

King Regards

[DDAAMMIIRR · Accepted solution]

Hello everyone,

I find a sollution for my problem.

In Memory-Properties-General-Implementation I changed from Block Memory to Look-Up Table and I successfully compile memory.vi and run it.

I made change as you can see on picture:

Just, can you tell me is there any 'bad properties' and limitations with using this kind of implementation memory (Look up Table) ?

King Regards

[Andy-C]

Hello,

You should take a look at the following document for more information about the various memory options available on the FPGA. In general, LUTs are a suitable memory option if you don't have much to save but need to access the data between clock domains.

Storing Data on an FPGA Target (FPGA Module)

http://zone.ni.com/reference/en-XX/help/371599H-01/lvfpgaconcepts/fpga_storing_data/#Memory_Items

Let us know if this helps!

Best regards,

Andy C.

Applications Engineer

National Instruments