problem, timed loop, cRio system

[zerosun]

I use a timed loop on a cRio (9014) target and i like to check the loop cycle time. I operate the system in scan interface mode, with an NI 9403 DIO Module. I use a timed loop with a shift register and a not in order to toggle the DIO0 output.

I monitor the output with an oscilloscope and it works for a loop cycle equal greater than 10 ms for some reason it doesn’t work for smaller time cycles. I would expect that I could control the loop in microsecond steps and so the DIO output too.

Labview 9.0.1 sp1

LoopTimingSource: 1 MHz Clock

Advanced Timing Attributes: deadline -1, timeout -1, offset 0, structure name l5...

processor assignment: mode automatic

action on late iterations: all checked

 

Does someone now what I am doing wrong?

Regards Thomas  

[ErnieH · Accepted solution]

The scan interface mode on the fpga is a fairly slow interface. If you want high speed I/O, you need to program the FPGA yourself. Even if you only pass through the FPGA I/O directly to the FPGA without any additional processing, it will be faster than the scan mode. Here is a link to a app note.

http://zone.ni.com/devzone/cda/tut/p/id/7338