pipelining

[tlin067]

Hi there, just a theoretical question about pipelining in SCTL's in FPGA. On the help sheet http://zone.ni.com/reference/en-XX/help/371599D-01/lvfpgaconcepts/fpga_pipelining/

i see you can use shift registers which after a certain latency will give an output from each sub VI each loop cycle. 

However in the diagram it shows that the first valid output of sub VI 'C" occurs with the 3rd output of sub VI 'A'. 

Is it correct that the output of Sub VI 'c' uses information from sub VI 'A' that occured 2 cycles earlier? If this is the case and I want to perform real time signal processing will there always be this delay in my final output???

If you could help me out it would be sweet!

Cheers

[jcarmody]

Yes.  Each VI runs during every cycle of the loop, but the input to B isn't related to your process until the 2nd cycle, and the input to C is likewise meaningless until the 3rd cycle.  You'll always have this delay in your final output, but your loop can run faster.

j 

Message Edited by jcarmody on 01-08-2009 04:22 PM

[tlin067]

So the code is now not executing in parallel? Is there a way to find out how long each operation in a loop takes? And to find what the critical path is?

[RavensFan]

The 3 subVI's are all executing in parallel.  But any given piece of data will require 3 loop iterations and go through subVI A on the first loop iteration,  B on the 2nd, C on the third.  Concurrently a new piece of data can be generated to go through A on the 2nd iteration.

The overall loop iteration time will take whichever subVI takes the longest.  So benchmarking each subVI will be useful and needed to balance the performance of each subVI which will reduce the overall loop iteration time.

[tlin067]

is benchmarking just analysing each individaul sub VI and working out the individual timing?

[RavensFan · Accepted solution]

Basically, yes.