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pipelining in FPGA Rio

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Just a simple question about pipelining. I have a simple computation. What would be called an inner product of two vectors X1 and W1 giving X1' X  where ' is transpose.

I have the program attached. Could I improve this program by introducing a delay after the multiplier (ie a shift register)?

Is that all I could do? I'm quite new to this but just need some pointers.

 

 

Thanks

 

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Accepted by topic author tomnz

Hi Tom,

 

It is unclear what you are trying to do from the code you posted.  It looks like you are multiplying two numbers together, and adding this product to the previous iteration?  I am unsure why are would want to add a delay as well.

 

If you re-post with a more detailed explanation of what the problem is, , someone may be able to assist you much better.

 

Thanks!

Ryan C.
Applications Engineer
National Instruments
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