pci bus emulator

[Slavik]

Hi!

I'm trying to write a program in LabView to emulate the signals of PCI BUS, accordingly to PCI Local Bus Specification.

I'm supposed to program NI-7831R Reconfigurable FPGA modul, with this program to emulate all the signals of PCI BUS.

Does anybody knows any VI's that I can use to complete the tast, and save some time, I would be very grateful.

Or maybe some tutorials or tips, how to produce such signals.

[Christian_L]

Due to the timing and clocking of the FPGA and the digital output signals on the 7831R I think this may be difficult or impossible. The FPGA operates with a basic clock rate of 40  MHz or 80 MHz for simpler FPGA diagrams. All operations including I/O are performed on a clock cycle. This means any signal that is generated can be updated at the clock rate or an integer fraction of the clock rate.

For the basic 40 MHz clock rate we can update signals at 25 nanoseconds, 50 ns, 75 ns, etc. This equates to update rates of 40 MHz, 20 MHz, 13.33 Mhz, etc. For the 80 MHz cl,ock rate these rates double. Given what I know about the PCI bus I don't think that this will be adequate to emulate the signal timing of the PCI bus communication.

[Slavik]

Hi,

Thanks for your quick response.

From what I have checked in PCI BUS Specification, the working frequency is 33MHz for most of the PCI peripherals, and 66MHz for High Performance peripherals.

It will be enough for me to make an emulation for 33MHz BUS. So I guess that it will be possible to work with this FPGA module.

I would like to hear your opinion.

Thank you,

P.S.

Here is the link for PCI Local BUS Specification that I have found:

http://www.ece.mtu.edu/faculty/btdavis/courses/mtu_ee3173_f04/papers/PCI_22.pdf

[Christian_L]

The problem is that the FPGA won't be able to update signals at 33 MHz. It can update at 40 or 20 MHz, but not at any rates in between. Each clock cycle of the FPGA is 25 ns (40 MHz clock rate). So it can update any of the digital output lines at multiples of 25 ns (25, 50, 75, ...), but not at 30 ns intervals which would be required for the 33 MHz rate.

[jdigiova]

You may be able to use a new feature in the LabVIEW FPGA Module version 8.0 called Multiple Clock Domains (MCD). MCD allows you to designate different portions of the code to run at different rates. For example, you can compile a normal while loop at 40 MHz and a Single Cycle Timed Loop (SCTL) can be compiled to run at 60MHz. The clocks that can be used to drive a SCTL are called derived clocks. These derived clocks are generated from a base clock. For the PXI-7831R the base clock has a rate of 40MHz. You cannot get a perfect 33MHz clock from a 40 MHz clock, but you can get 33.043MHz (40*19/23). Any portion of the code that had to run at that rate should be used in the SCTL configured to use the derived clock. Now there are other factors that may also hinder this application. Specifically you may not be able to actually generate nice TTL signals the rate of 33MHz. The signal will get degraded with various cables and impedences of the system you are connecting to.
Regards,
Joseph D. National Instruments