In LV 7.0, the state machine is a design pattern (and probably the most powerful pattern for ATE) in LV 7.1 there is even a state diagram toolkit which will help code the states for you. Essentially a state machine is a while loop with shift register holding a state (often an enumerated type), the states are placed in a case structure and the output of a state is the next state to execute, unless it is the terminating state which is passed to the condition of the loop, ie while (state != terminal state). The shift register is initialized with the initial state. This is a really nice method for controlling a sequence of events specially in a data-flow program such as labview. It also allows for easy initialization and safe shutdown of your test and will handle errors with ease. You can replace any sequence with a state machine and gain the flexibility of out of order sequencing, which is not possible with static sequence structures. I also think the state machine promotes good modularity of code.
Paul