LabVIEW
labview Fpga Consumer loop speed
Hi kazmi,
@kazmi12 wrote:
I have attached my code.
Whih is fine. It would be even better if you would attach the whole project including the lvproj file as it contains all the FPGA related definitions (like FIFO)!
@kazmi12 wrote:
On the PC side, I am using producer-consumer architecture to get and analyze my data. I am getting data in producer loop using DMA FIFO and then analyzing it in the consumer loop. In the analysis, I am trying to save the last 2 second data and at every second the old data goes out and new data comes in. I have a threshold value set on FPGA so when the threshold will reach the channel will close and I will have the last 2 sec data to analyze. The data transfer between the producer-consumer loop is done by queues.
Why do you try to read exactly 1000 samples from the FIFO when your FPGA can stop writing to the FIFO at any time?
Why do you wire a "1000" constant to the FOR loop in the producer loop? Don't you trust that autióindexing input tunnel?
Why do you wire the "i" terminal of the consumer loop to the FOR loop count input?
Why do you try to read 50k samples from the queue in the consumer loop in the inner FOR loop?
Why do you initialize that shift register in the consumer loop to hold 100k samples? (Samplerate=50kS/s)
When the outer FOR loop iterates 10 times you are already trying to read 500k samples in those stacked FOR loops!
There is so much unclear/buggy in the PC code you really should cleanup and document/comment the code much better…
Hi kazmi,
As GerdW pointed out, your PC-side code could be improved a little.
Some additional points that might help:
- You could make the datatype of the Queue an array of fixed point values. Then you wouldn't need the For loops at all.
- I'd suggest using a different method (not the local variable) to stop the Consumer. The way it is now, any delay in the consumer loop will lead to not processing the last (potentially many) iterations, including the block that actually exceeded the threshold.
- An example might be sending an empty array in the last iteration of the producer, and if in the Consumer the array dequeued is empty, stop.
- If you want to store a circular buffer of samples (for the last 2s), you might find it easier to use a fixed insertion point and Rotate 1D Array. Then you can rotate by the array size, if you wanted, in order to make it more flexible if the block size changes
- As GerdW already pointed out - if you use timeout = -1 for the DMA Read and you don't receive ALWAYS blocks of 1000 samples, the loop will hang on the last set. Either:
- Make sure that you always send blocks of 1000 points from the FPGA, or
- Don't use -1 as the timeout, set a more reasonable value and check if the timeout was true. Note also that the array is empty when timeout is true, so this could be a termination condition in combination with my point above (empty array) if you know it will only timeout when the threshold has been exceeded.
