labVIEW FPGA

[sumsum]

Hi,
     I have a doubt with timed loop....in our project ,at  the  output  of pi/4 dqpsk modulation, the frequency should be 18khz....but in the timed loop block, the internal clock (timing source)is 1khz and 1mhz... and we purchased NI h/w with the FPGA, NI PCI 5640R...Is there any provision in the FPGA to change the clock to 18khz???

[Mathan]

you have posted same question in all the forum. stick to a single post.

[Sorooshster]

Hi Sumsum,

I'm not exactly sure what your doing with your modulation but if I understand your question correctly you are wanting to slow down the rate that the single cycle timed loop is executing.  You can simply use a loop timer to do this or you could decimate the timed loop rate.  The loop timer would be the easiest way to do this, you just put a timer in the loop and tell it how long to wait before executing.  To decimate the loop rate you will need to use a shift register and case structure inside your timed loop.  There is an example of this in the knowledgebase linked here.  This knowledgebase deals with a separate issue but shows how to decimate the loop rate as part of the solution.