jitter of output digital waveform with external clock

[Vasilich2004]

Hi,

I need to generate digital waveform with 20 bits pattern * 1000 times. Digital waveform must be sync with 1 MHz external clock.

It is not big deal.

But there is additional requirement that digital waveform has jitter < 200 ps. It can be delayed for couple ns but it must be very stable.

Can anyone point me on that parameter? Or share your expirience?

Thanks!

[jaced]

HI,

If I understand you question correctly you are concerned about the clock jitter for your device. If my understanding of you question is correct then this information will be available in the specifications document for your device. If I am incorrect can you please post back with which device you are using as well as perhaps a clarification on the jitter you are concerned with.

[Vasilich2004]

JaceD

Let I simplify problem ...

External clock is ideal. It comes with 1MHz rate.

The buffer of DO has 5 bits, like 10101.

DO generates these 10101 with some delay but delay should be stable, let say from 3.2 to 3.4 ns (or jitter <= 200 ps)

Thanks, Andrei.

[jaced]

Hi Andrei,

Thank you for the clarification, I still would like to know the device that you are using in order to correctly identify
a. if this will be possible
b. what the best way to accomplish this task will be.
Thank you in advance for posting your device.

[Vasilich2004]

JaceD,

I didn't chose device yet. But it can be one of

- DAQ of M-serie (let PCI-6251) (I am not sure that DO channel can use external clock)

- PCI-6534 (I know that DO uses external clock)

One more time, I would like to load 5 bits (10101) to buffer of digital channel, ideal generator generates 1 MHz clock, and I would like that DO generates 10101 and 5 fronts have pre-defined delay +/- jitter, for example 3.5 ns +/- 100 ps.

Actually, I met notice about 200 ps jitter in FPGA card, like PCI-7831R. But I am not sure.

Thanks,

[jaced]

Hi Andrei,

Thank you for the information I will use the PCI-6562 as an example. As you can see on page 24/30 in the specifications document the delay from a trigger to digital output is 34 sample clock periods +85ns, you could use a faster sample clock and “pad” you data to match the needed output in order to lessen this effect. There will not be a delay between clock edge and data generation but if you wish to perform data delay with an HSDIO you will need a clock speed of 25MHz or greater, in which case you could perform the same data manipulation mentioned earlier. It is also possible to perform a clock delay which is specified on page 6/30 in the specifications document. Keep in mind that this is not the only card option I simply selected it as an example

[Vasilich2004]

JaceD,

I looked on PCI-6562.

Definetely, I am not interested in "34 sample clock periods +85ns" parameter. That is dealy. Moreover, 34 085 ns (I need 1 MHz) can be unacceptable delay in my case.

I also found once place with something like jitter. It is MAX delay channel to channel  +/- 500 ps (page 7). But it is not my case.

So I don't see that PCI-6562 can help me. Maybe I am wrong?

Thanks, Andrei.

[Speedy_Badger]

Hi Andrei,

I believe the specification you are actually looking for here is the jitter of the sample clock, rather than the trigger delay that Jace was quoting.

If you look at Page 9 of the specifications manual for the 6561/6562, you will notice the "Generation provided setup and hold times" entry. This corresponds to the minimum setup and hold times we guarantee relative to the sample clock. With clock signals greater than 25 MHz you can use data delay to shift the setup and hold times according to your needs. You could also delay you clock signal. The jitter and skew are already included in these specifications.

So for instance, with the 6562 we guarantee a setup time of tp - 2.2ns, where tp is the period of your clock signal, and a hold time of 1.1 ns. With your 1 MHz clock we will see the following specifications:

tp = 1 us
Setup time = 1 us - 2.2 ns = 0.998 us
Hold Time = 1.1 ns

I hope this clears up any confusion regarding this device.

Regards,

[Vasilich2004]

Chris hi,

Yes, you correct. I am looking on data jitter that depend of external sample clock.

Figure 3 on page 9 is more interesting.

My understanding is that I am interesting in a range between Tph and Tpsu ranges. The range should be <= 200 ps. Also jitter Tph will increase the range.

It looks again I don't see correct information.

Also maybe you know another card?

Thanks, Andrei.

[Speedy_Badger]

Hi Andrei,

Tph on figure 3 is defined as tp - 2.2ns as we discussed earlier. The data jitter, along with channel to channel skew, is already taken into account. We don't specifically spec the data jitter since we have made this calculate for you. It is safe to say that the data jitter involved in tph is less than 200 ps however this is not a standard spec we provide.

As for additional board recommendations, what is your application? The 6562 is designed for LVDS applications. The 655x series is highly recommended for high speed TTL based applications. If you reference the 655x manual you will notice similar or better specifications in regards to setup and hold times, which again already take into account data jitter and skew.

I am curious as to why you would like the specific values documented. We provide the current specifications so that you do not have to use the individual statistics to calculate numerics such as the setup and hold times. Is there something specific you are trying to do here? You mentioned a simple example earlier, what is your actual application?

Regards,