increase sampling rate using rational resampler in FPGA

[hsw9797]

i can't understand process of resampler

i know as interpolation is that obtaining sample and zero padding and apply low pass filter 

because of resampler is black box, i can't understand why VI need input output valid node and other things.

and what happens? if there is silghtly difference sampling rate that differ what we set in resampler VI between RT and FPGA?

Here is my FPGA 

ex i send sine data from RT to FPGA and emit sound from speaker 

2000Hz (RT) -> 25600Hz (NI data rate).  L = 64, M = 5

in RT, i send one sample data to FIFO with rate 2000Hz using Timed Loop. 

but is not work.......

what is the problem.....

please help me.... 

[wiebe@CARYA]

That image is shrunken beyond being usable...

[hsw9797]

읽기 = read 

[hsw9797]

or this VI

[hsw9797]

i send one sample data from RT and FPGA with 2000hz sampling rate. (value of data is 1)

and FPGA read data from FIFO with ex 4000hz sampling rate. 

in this situation, i think Final data transfered to module have (1 0 1 0 1 0 1 0)

actual speaker emit sound like this. 

but i don't understand timeout value 0 and -1 

"A value of –1 prevents the function from timing out, so the function completes execution only when data is available for reading. A value of 0 indicates that the function does not wait"

what is the wait? 

and in my situation, if i set timeout value 0 or -1 in FIFO read, what is the different and what will happen?

[Terry_ALE]

0 attempts to read the buffer no matter what. If there is nothing at that moment, then timeout outputs true.

-1 indefinitely waits until there is something to be read.

I think this is simple enough such that code could be made to confirm the above and better understand it.

[hsw9797]

Thank you for your reply...

Could you take a look at this problem?? 

https://forums.ni.com/t5/LabVIEW/increase-sampling-rate-using-rational-resampler-in-FPGA/m-p/4226210...

i'm doing signal processing in FPGA and RT

[Terry_ALE]

Two questions:

1. Is the resampler needed?  Can you send data at the AO sample rate?

2. Can you do without the SCTL?

When you put functions in an SCTL, they sometimes need handshaking terminals due to latency or throughput.  For example, even if they can process one sample per cycle, they may need startup time.  See https://zone.ni.com/reference/en-XX/help/371599P-01/lvfpga/rational_resmpler_fltr/ (search for latency).

P.S. Cool to see LabVIEW FPGA in Korean!

[hsw9797]

Thank you 

 1. No FPGA Data rate and RT data rate is silightly different

in my situation, Data rate of FPGA have to be higher than RT

now i'm just make low pass filter to interpolate with Low API. So i have to do convolution.......i made buffer and multiply buffer and filter but where is add Array Elements...? hahahahaha