how to synchronize with single cycle timed loop

[Paul_Conaway]

From within a SC Timed Loop I need to send some sort of synchronization signal back to the Host computer. I cannot set an interrupt because it takes two cycles to execute. I tried to get around this limitation by setting an occurance.  Another loop that is not a SCTL is waiting on the Occurance and sends the interrupt. This doesn't work either because signals cannot cross "timing domains". Has anybody figured a way around this?

Perhaps one could toggle an output bit in the SCTL, externally wire it to a different input pin, then have the 'regular' loop sense that and send the interrupt.

[Andrew_E]

Hi Paul,

Is this SCTL on the Real-Time Controller or on the FPGA? Outputting to a physical line may take much longer than a clock cycle depending on the clock used. Have you tried writing to a datasocket and reading it on the host computer and send your execution signal that way?

[Paul_Conaway]

Andrew,

Sorry that I didn't mention it but the target is an FPGA on a PCI-8713. I am running the clock at 26 MHz.

The main purpose of the loop is to produce a complex sequence of interrelated and fully adjustable timing pulses for a radar system.

I can program in a number of repetitions of a given sequence. I am looking for a way to inform the host that it is doing the last repeat.

Paul

[Andrew_E]

Hi Paul,

I would suggest using a dma fifo to transfer a signal back to your host vi from the fpga.

[Paul_Conaway]

Andrew,

I have another FPGA application that uses FIFOs. It is a SPI bus master state machine using SCTL. FIFOs in both directions work well and reliably. The only problem is that I notice some jitter which I write off to the DMA and perhaps some Memory allocation that the Operating system gets involved with now and then. I had been thinking of using a FIFO here in this timing application as you suggest, but I was holding off to see if something better (more deterministic) might show up. I realize that with Windows even an interrupt is a shot in the dark. Because you fellow wizards have come to the same conclusion, i.e. there is no other or easy way to do it, I think I will go ahead and implement it. I believe that I can have the host wait for a message from the FIFO and with a timeout too, rather than poll for it.  Thanks