how to set startup vi in fpga

[suni]

Hi,

I am using labview 8.6 with Crio 9014 and NI 9215, 9263, 9403 C series modules with 9103 chassi. i have 2 fpga vis in my project and 1 RT host vi. How do set up one of the FPGA vi (this vi ouput default values using analog output module) to run  automatically during the power up of the CRIO 9014? Then as soon as i start running RT host vi, program should stop first FPGA VI and start running the second FPGA VI.  Is there way to do this? Thanks very much.

[Ipshita_C]

Hi Suni,

To answer your first question, the first FPGA VI can be set up to Run When Loaded by going to the FPGA target in the project explorer, right-clicking on it and going to Properties.  In the General tab check the option where it says Run when loaded to FPGA. Regarding the second question, are you looking to stop your first FPGA VI through the RT host VI? Are you also looking to run the second FPGA VI though the RT host VI?

Ipshita C. 

[suni]

Hi

Thanks for the reply.

 I want one FPGA VI to start running as soon as power is avilable to Realtime target (crio). Can i do this If i select Run when loaded to FPGA? Yes I want to use my RT host vi to stop first fpga vi that is running and start running the second fpga vi. Thanks.

[Ipshita_C]

Hi Suni,

An FPGA VI will not run unless it has been compiled and the bitstream has been generated which can happen only after the Xilinx compile server has been called. so when you select the option Run when loaded, the FPGA VI will run as soon as it has been loaded to the FPGA target. You can add another step to this--go to the RIO device setup in Start >> Program Files>>National Instruments>>NI-RIO>>RIO Device Setup and ensure that the option Autoload VI on device powerup is checked. You can also specify the bitfile to download to flash which will prevent compilation every time the FPGA VI runs. You can do this by following the instructions in this knowledgebase. In regard to your second question, you can stop the first FPGA VI by passing your FPGA reference into an Invoke Method node and invoking the Stop method. Regarding starting your second FPGA VI from the RT host, you can load the precompiled bitfile in the FPGA reference or the VI itself. It is more of a programming/design issue. You have to set up a condition for the first FPGA VI to stop running, only then you can start the next one by loading its reference--if you just precomile the second one and load the bitfile into the reference it can run the VI but will not compile it. Hope this helps.

Ipshita C. 

[Newton2this]

Hi, I have a PXI-1042Q Chassis with PXI 8108, 7842R(FPGA), and 6259(DAQ) installed.  If I want to run a Host VI that I have save to my RT target (after enabling my RT target's VI server) and downloaded an FPGA VI to flash memory using RIO Device Setup can I get the downloaded FPGA VI to communicate with the Host VI with or without DMA??  The whole idea here is to create a 'stand alone' application that can be linked by ethernet or TCI/IP.  Any suggestions would be greatly appreciated.  Thanks!!  John

[Charlie_P]

This is a duplicate post.  Please see:  Re: launch LV Real-time on target programmatically

[Newton2this]

What I am wondering is - is there a way to send a 'heartbeat' of some kind (via TCP/IP using a network shared variable for instance) so that I know that the FPGA is communicating to the Host?