hdl node parameters

[sparkymark567]

I am a beginner in VHDL, but...... is there a bug here in LabVIEW?

In the configuration Window of a HDL node, I have selected the following parameters:

Name: X,  direction: in, type: bool, length: -

Name: Y,  direction: in, type: bool[], length: 0;

Name: Z,  direction: out, type: bool length: 0;

LabVIEW then generates:

entity hdlnode  is
   generic(
      ClockFrequency : Integer := 40000000;
      InSingleCycle : boolean := false
   );
   port(
            clk : in std_logic;
            reset : in std_logic;
            enable_in : in std_logic;
            enable_out : out std_logic;
            enable_clr : in std_logic;
            X : in std_logic_vector(0 downto 0);
            Y : in std_logic_vector(1 downto 0);
            Z : out std_logic_vector(0 downto 0)
   );
end hdlnode;

I am confused why LabVIEW has implemented X and Z as  vectors. This does not seem correct, because:

Name: X, direction: in, type: bool[], length: 1 

and:

Name: X, direction: in, type: bool, length -

both generate exactly the same VHDL code.

Why does LabVIEW behave in this way?

I was expecting, LabVIEW to generate something like:

X : in std_logic;
Y : in std_logic_vector(1 downto 0);
Z : out std_logic;

Thanks
Mark

Message Edited by sparkymark567 on 11-02-2009 05:35 AM

[Mark_SAI]

Hello Mark,

Does the compiled code work?

[sparkymark567]

I am suggesting that there is a bug in the way that LabVIEW generates VHDL code from the configure HDL node dialog.

Type Boolean causes LabVIEW  to generate code for a VHDL vector of length 1 (i.e. an array) and in my view it should not be a vector. If on the other hand there is some reason why LabVIEW can only use vectors, the option for a Boolean should not be in the dialog.

But as I am a beginner in VHDL, I can not say for certain whether it is a bug.

Does the code generation also seem incorrect to you? explanation? or please raise a CAR number so the bug will get fixed.

Thanks

Mark W

Message Edited by sparkymark567 on 11-09-2009 07:11 AM

Message Edited by sparkymark567 on 11-09-2009 07:12 AM

[muks · Accepted solution]

Is a CAR generated?

[Mark_SAI]

This was reported to R&D (ID:196209) for further investigation.

The reason I ask if it compiles and works ok, is because as far as I can see

 X : in std_logic_vector(0 downto 0);

and

X : in std_logic;

are similar things.

[sparkymark567]

You can wire a boolean into the HDL Node with VHDL vector of length 1, yes.

...but the dialog forces you to use a vector in VHDL (or create a new variable and copy the value in). Either way works fine, but you  have to write more VHDL code, than would otherwise be necessary.

Thanks

Mark W