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here is my scenario//

i have two adc inputs in my fpga module..(i am using compact RIO 9074,which has NI 9234 as its adc input channel.)

what i want is the sample by sample inputs from the FPGA program to the RealTime Program so that i can use it for my purposes..

since i have two input ADC channels,i have put both of them into a build array,the output of which goes to a for loop which has a FIFO,(target to host,FXP) that send the elements to the RT.
now,while recieving the date from the,i want sample by sample from each ADC channel.

if i do decimate array,i am getting an array of lets say 'n' the next iteration i am getting a new set of 'n' elements.which is not what i want.i want one by one all elements of the array..

how to solve the issue..??

please send me an attached FPGA and RT code so i could actually see where i went wrong.

we could also have a talk using team viewer if that is convenient to you.


i am attaching png files of the fpga and rt programs..please have a look..


thank you.!


contact me ---

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Message 1 of 4

Re: fpga

If I understand you right, you want each pair of samples one at a time, but you're getting a variable number of elements from the FIFO read each loop iteration.


Since you know you're always writing 2 samples each FPGA loop, would something like this work for you?



Grabs 1 or more sets of elements and the shift register tells the next loop how many to get next time.  Results are pipelined in the 2D array for processing.  This lets you slow down your loop too.

--Using LV8.2, 8.6, 2009, 2012--
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Message 2 of 4

Re: fpga

yes..u understood me right.i want each pair of samples per loop and not more than one pair. but i didnt understand what you did there..isnt there an easier,standard solution??.i am new to lab view..but i guess,there must be standard procedures to get data sample by sample from the fpga..


let me know..


thanks..Smiley Happy

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Message 3 of 4

Re: fpga

The FPGA and the cRIO will run at different loop rates and there's no simple way to sync them up.  Usually the FPGA is capable of looping a lot faster.  The code above simply reads all the FIFO data and breaks it into n sets of x readings.  Take a look at DMA FIFOs and pipelining to understand how that loop works.

--Using LV8.2, 8.6, 2009, 2012--
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