fpga sampling rate

[charlie87]

Hi guys !

I am starting with LV and FPGA and I am not sure about sampling. I am going to try to explain my question with the examples from LV installation. See pictures below.

In one case, there is used sequential diagram and in the first frame there is made clock or time delay to establish sample rate. This task runs repeatedly in while loop.

In another case, there is used no time delay and input data are read in loop and write to DMA FIFO. What is the sampling period here ? I think that the loop rate is much higher than the rate that input data are changing so one value can be write to FIFO a number of time. Or is there some kind of synchronozation ? 

[viScience]

The best way to define loop rates is to use a loop timer or a timed loop structure.  Otherwise the FPGA will try to be running at the top level clock rate set in your project, which is typically 40MHz.  If you put your code in a timed loop then LV FPGA will calculate to see if all of the code will execute at the rate specified. 

[bbb456]

I have another question...

I have A/D module NI 9232 in my cRIO running on maximal rate 102,4 kHz. When I use timed loop structure or loop timer to define rate e.g. 50 kHz.

It is downsampling, isn't it ? So some kind of LP filter should be used ????????????????? 

[viScience]

If your 9232 is internally sampling at 102.4KHz than it is internally hardware filtering the signal to prevent aliasing.  You can read from the device at any rate you want up to 102.4KHz.  If you are only reading at 50KHz then you will get a overrun flag but you can disregard it if you don't care about the missing samples.  Applying a software LP filter would only depend on whether your signal has regular noise in it that you would like to filter out.  If your signal contains significant energy > 25 KHz then you will have a problem and would need to sample faster.

[PackersFan]

Those two pictures are showing two different methods of timing because they are using two different modules.

Some modules (like Mod1 from your first picture) will actually have an internal sampling rate.  In that case, the I/O Node read will block until new data is available, thus timing the loop.

Other modules (like that shown in your second picture) do not run at an internal rate when used by the FPGA. Instead, they simply take a sample every time your diagram encounters the I/O Node.  Thus your loop controls the sampling rate.

The method you will use depends on the module.  If the module exposes a Data Rate property, you should use it.

[Zody]

Hello Charlie,

Indeed, National Instruments has two types of devices:

1. Devices like 9237, 9233, 9234 have an Analog to Digital converted called Delta Sigma. This kind of devices can not have any sampling rate, but gives you the possibility of choosing. Usualy 9237 and 9234 have a Master Base Clock that is around 13 MHz and the sample rate that you can choose is derived from that clock.

You can read more about that in this manual https://www.ni.com/docs/en-US/bundle/ni-9234-getting-started/page/overview.html at page 16.

The advantages of this Delta-Sigma ADC are:

a. very good resolution - 24 bits

b. antialising filters that are automaticaly set when you choose your sampling rate.

2. Other type of devices like 9205 and many other, have a SAR ADC (succesive aproximation analog to digital convertor). Usualy this devices have up to 16 bit resolution but you can set any sampling rate you want (within the specs of the device). The sample rate is given by the rate of the while loop where you are reading the AI.

I invite you to use an architecture for cRIO that you can download here https://forums.ni.com/t5/Example-Code/Reference-Application-for-NI-CompactRIO-Waveform-Acquisition/t... 

Basically this comes with examples that will show you how to program an acquisition on FPGA when you have delta sigma modules, SAR modules or even when you have to syncrhonize multiple modules.

If you have more questions or concerns please post them here.

Kind regrads,

Ion R.

[charlie87]

Thanks. It is exactly what I wanted to know and understand.

So, when I use NI 9232 A/D converter which is Delta Sigma device I cannot set whatever sampling rate I want to ? I mean I can set only the rates which are specified in datasheet such as 102,4 kHz,... to 0,98 kHz. I cannot use timed loop to get sampling rate e.g. 48 kHz ? Please confirm that I am right 🙂

This is a little bit tricky because I have this module NI 9232 and I am supposed to do resampling from 102,4 kHz to 1.28 Hz. So, what are the options to get lower sapling rate than the minimal one available in datasheet which is 0.98 kHz ? 

[Zody]

Yes, you are right, you can not have any sampling rate, only to choose ones available in the "data rate node".

But you can sample it with the lowest possible and than just decimate the datas until you gate to the rate needed for you.

Kind regards,

Ion R.

[charlie87]

I suppose that decimation LP filter due to aliasing is not needed, is it ? 

[Zody]

I am not sure I understand your question, can you rephrase it please?

Ion R.