fpga: Problem compiling FSM

[HelpMeJebus]

: Hi all again,

I'm still working on optimizing my encrypytion code for maximum throughput, and decided to more closely structure my labview VI like a FSM from vhdl. The code consists of a SCTL with a case structure inside to represent the states. Because the design relies heavily on BRAM, there are some cycles dedicated entirely towards reading the data out of the BRAM because as it says in the help, the output is only valid during the next clock cycle. It works when implemented on the dev computer, but fails to compile with the statement:

"The selected object has an embedded shift register that makes the output on a particular loop iteration correspond to the inputs from the previous iteration."

Logically, the way it is structured makes sense to me and obviously works on the PC, so I am unsure what labview is asking. Does anyone have any experience with the error and how to fix it?

Thanks!

[Dragis · Accepted solution]

You're almost there ; )

The error is being generated because you have the memory reads inside the case structure and the LabVIEW compiler isn't smart enough (yet) to make that scenario work. In general, it would require adding additional muxing logic on the output of the left end of the shift register which could cause timing issues. In your case, moving the reads outside the case structure and having them wire directly to the shift registers should work. It doesn't hurt to read from the memories every cycle.

[HelpMeJebus]

Thanks Dragis!

After some tampering, I finally moved all the memory blocks outside and it's working like a charm. By the way, the picture was very helpful as well. Thanks for taking the time to help!