converting continous elements in array using fpga?

[SaraBaber]

Hello

I am sending my data from RT to fpga!. at RT side I have converted my 2D array(3 rows and unknown number of col depending on spline iteration) in 1D and fed into the write FIFO to send to fpga. at fpga side I am getting elements from read FIFO! there I want to create three 1D arrays with row1, second with row2 and third 1D array with row3..how can I do that. is it possible to know where the row is finishing and when does it start displaying next row?

or its not possible without knowing the col size? If yes than lets assume that col are 1084.. then how can we do that?

Sara

[crossrulz]

An FPGA has to have set length of arrays.  It is hardware after all.  If you assume the split is always as the same place, you could use Array Subset 3 times.

[SaraBaber]

Thanks but is there any way to know when the elemets of next row has start been displaying at fpga side?

SAra