clock divider FPGA C-RIO

[AitorArrieta]

Hello everybody,

I am using the FPGA of the C-RIO 9082. However, when compiling, a timing error is launched, and the problem is that there is a 862 ns delay; the solution could be to reduce the clock that triggers the loop; the problem is that this clock cannot have a smaller frequency than 2.5 MHz. Is there any possibility to divide this frequency??

Thanks in advance,

Aitor

[BFeigum]

Yes you can! Create a Derived Clock in your project. Now use this new (slower) clock as your clock source in your FPGA timed loop. You can also select the new clock as your Top-Level clock.