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04-04-2013 02:58 AM
hi,
i want to control chassis DSUB pins throught verilog coding by adding CLIP on my FPGA project. i have chassis 9103. how can i learn, chassis DSUB pins connected with which FPGA pins (chassis 9103 virtex II) ?...
Best regards..
04-05-2013
12:07 PM
- last edited on
03-15-2024
02:16 PM
by
Content Cleaner
Hi Davut,
If you are interested in the pinouts of the DSUB connectors on our FPGA backplanes, we include that information in the CompactRIO Module Development Kit.
Additionally, if you wanted to directly access FPGA pins, you could use a SingleboardRIO with a RIO Mezzanine Connector.