LabVIEW
cRIO 9039 Timing error compiling FPGA when using 9215 module, but only when in slots 7 or 8
This had my colleague and I stumped for most of today!
The FPGA code that we have only does one thing. In a while loop it reads an analogue input from a 9215 module in calibrated mode and writes it to an indicator.
When the 9215 module is placed in slot 7 or 8 in the project, the following timing error appears at the end of every compilation:
"LabVIEW FPGA: The compilation failed due to timing violations.
Click the Investigate Timing Violation button to display the Timing Violation Analysis window."
We tried adding loop timing, using a FIFO, installing updates, different versions of windows, 3 different machines, turning it off and on again... to no avail. The only thing that "fixed" the problem was moving the module in the project to slots 1-6. Has anyone else come across this? Have I found a bug or a feature?!
We are running LabVIEW 16.0f5 (32-bit). The compilation tool being used is Xilinx Vivado 2015.4 (64-bit).
Seems like a bug to me. I tried compiling the code on the cloud server and got the same timing violation (with LV2017). I also tried pipelining the write to the control, but it also failed. Recreating the project configuration from scratch also results in a timing violation. The same code compiles successfully when targeting a cRIO 9035 + 9215 in slot 8. A cRIO 9039 with a lowly 9201 in slot 8 also produces a timing violation, so it definitely seems like a bug with the 9039 slot 7/8.
The timing violation results indicate a 0.00ns requirement was missed, which then refers to an internal IO port of dio78. The xilinx log has more info (attached), but is a bit beyond my understanding. A 0.00ns requirement does seem odd though.
