Xilinx FFT function: how to feed values to it one at a time?

[count3r5tr1ke]

I am using LV2012 FPGA with the RIO Evaluation Kit (sbRIO-9636). I have a 1d array of U16 that I want to put into the Xilinx FPGA FFT function.* It originally had a while loop around it, but when I tried to compile it told me that function was only supported inside a single cycle timed loop so I changed the while loop to an SCTL.

But now when I try to compile, there's a "code generation error" screen that says "You cannot include this function in a For Loop when the For Loop is inside a single-cycle Timed Loop." The purpose of the for loop is to feed the array values one at a time to the FFT function, as required. Is there an alternate way of doing this?

*(I realize it would be better to dynamically load the data onto the FPGA, but I'll just hardcode it for now because I want to make it as simple as possible at first just to get some graphs. I'm not concerned about optimization for now.)

Also, if needed here's the datasheet for Xilinx FFT: http://www.xilinx.com/support/documentation/ip_documentation/xfft_ds260.pdf

[count3r5tr1ke]

I put the SCTL inside the for loop, looks like it's actually trying to compile, hope it works. Soooo slow though.

[count3r5tr1ke]

Anyone know, if I offload the compilation to a remote server, do I have to keep my computer connected to the remote server the entire time?

[alcava.cr]

Hi there, you can remove the SCTL (you don't really need it unless you are acquiring data and the Array constant is meant to be replaced with an analog input).

[count3r5tr1ke]

Thanks for your response, however I tried it first without the SCTL and when I tried to compile, it told me the Xilinx FFT could only be used inside an SCTL. That's why I had to put the SCTL. 

[alcava.cr]

...then consider keeping the SCTL and use the Iteration terminal to feed the index input of the Index Array VI. That way you can get rid of the for loop.

[count3r5tr1ke]

Thanks, I'll keep that suggestion in mind. That code wouldn't fit on the FPGA, I assume it's because I need to store the array on the host instead, and make a shared variable for it?

Also, stuff that's inside a diagram disable structure doesn't affect the compilation, right? 

[alcava.cr]

The idea with FPGA programming is to have the benefit of hardware time acquisition and analysis, if this array is so big that doesn't fit on the FPGA then it would make more sense to keep everything on the RT side. In the case you are planing to transfer data here is an article that can give you a good reference.

Regarding the disable diagram, when LabVIEW compiles the code (before the creation of the intermediate files) the code inside is removed.

[count3r5tr1ke]

Good info, thanks

[count3r5tr1ke]

OK, I looked at that web page and I'd like to use programmatic front panel communication so I can store the array on the host and feed the values one at a time to the FPGA vi. In that case, what should replace the array constant on the FPGA vi? The rest of the variables have FPGA I/O items, but maybe the input array is different because the source of the data is the host, not the board inputs.

I created a new shared variable and called it "FFT Input Array" that I put on the RT microprocessor vi. Is this the right configuration? (other than the read/write control, I can't select the input array yet probably because it's not on the FPGA vi yet. It's hard to tell how the configuration should be, because all the other variables are going the other way (data from FPGA to host) .

Also, is this the right way to set up the host vi? The FFT input array has its own event case, while the rest of the variables are in another case.