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Why does expanding a timed loop always expand diagram in the same direction?

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I just noticed a wiring diagram behavior within LabVIEW 9 I really do not care for.  I have several parallel timed loops on my diagram and want to expand them a little to add some code within them.  When I drag one to one side to enlarge it, my entire wiring diagram expands to accomodate the drag.  However, when I expand one of the others into the newly created space, it AGAIN expands my entire digram in the same direction.  Why does this do this as there is already plenty of space to expand into created by the first "click and drag" operation.  Can this behavior be prevented?  If so, how?

 

Bill

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I could not reproduce the issue using a very simple VI with two timed loops. Could you attach your VI in this thread so we can see this issue?

 

Norbert 

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Norbert:

Sure.  Here's the code.  I forgot to mention that the timed loops were originally while loops that were later changed into timed loops, but see whether this behaves the same for you as it does for me.  And thanks for looking into this - I tried adjusting my autowiring settings, etc., but I can't stop this behavior, which is really annoying, especially when I have four parallel timed loops.  The other parallel while loops do not exhibit this behavior.

 

Bill

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Bill,

 

ok, now i see... my simple VI was not correct for the test since i had only some code inside the loops, not after them.

After seeing the issue in your VI, i again checked a simple newly created one and the behavior is the same. LV 8.6.1 behaves the same too. So obviously it is expected behavior.

I found no option which would deactivate this behavior.

PLease note that this behavior indeed does not occur with a normal while loop. So i assume that this behavior is created by management of the outputnode of the timed structure (i would think that timed sequence works the same)

 

Norbert 

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Norbert:

Again, thanks for looking at this issue.  It helps to have a "second set of eyes" to look through to understand an issue.

I'm not sure why you say that "LV 8.6.1 behaves the same too. So obviously it is expected behavior."  I thought LV 9 was a leap, not a refinement in code.  In any case, it's not just the output node side of the timed loop that exhibits the behavior.  It doesn't matter which way you drag and click to expand the timed loop, it expands the diagram.   Up, down, left, right, all expand the surrouding wiring diagram.  Is there a secret "CTRL" drag involved?

Anyway, it's nice to know my install of LV is not broken.

Thanks again.

 

Bill

 

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Norbert B wrote:

Bill,

 

...the behavior is the same. LV 8.6.1 behaves the same too. So obviously it is expected behavior.

...

Norbert 


Hmmm...

 

So any bug that makes past the next release is by definition not a bug?

 

 

 

 

Ben

Retired Senior Automation Systems Architect with Data Science Automation LabVIEW Champion Knight of NI and Prepper LinkedIn Profile YouTube Channel
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Bill,

 

the "feature" (this sounds better than "bug", does it? 🙂 ) only occurs in my system for wires and controls which are connected to the input/output nodes of the timed structures and only if the structure is enlarged in the horizontal range. It does not matter if the controls are in the same vertical range as the timed structure though...... So this is what i assume you think off when talking about "Up, down, left, right".

 

@Ben:

No, i don't want to say that: hey its been there for a while so it is no bug.

I just want to point out: Just because it does not work like i would expect it to work....is it really a bug?

 

Norbert 

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Norbert:

You are right about the up / down behavior.  I  agree with Ben, though, (and I am loosely paraphrasing and interpreting what I think he said) that any unexpected behavior should not be considered a feature when it really should be considered a bug. 

 

Ben:

So should I report this as a bug?  It's not of the crashing variety but if you are trying to keep your diagrams as small as possible while as large as necessary this does cause some effort to keep up with if you experience it.  It seems to me this is just a property that someone forgot to clear in the g code for the behavior of a click and drag operation on timed loop objects (click and drag = [CTRL] + drag).  The problem seems to me to be getting it on the list and high enough so the appropriate responsible party can uncheck that box before the next LV build and release...

 

BTW, I like your gif animation.  :smileyhappy:

 

Bill

 

In the Land of the Blind, the One-eye Man is King (even if that eye is blurry from many hours of wiring!)
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Solution
Accepted by topic author Bill_in_Detroit

Ah, the NI forum is a source of deep wisdom and knowledge 🙂

 

Please read this thread for a solution.

Btw. you do not need to set/reset this option everytime if you want only to have timed loops to have this disabled. You can set this option per structure after dropping it using the context menu. 

 

Norbert 

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Duh!  I turned off autogrow in tools>options>block diagram but was NOT aware that I could right click on the timed loop structure and turn it off there too.  It still doesn't explain why this occurs to the surrounding wiring, but I'll take it as "acquired wisdom" and move on.  Thanks, Norbert!

 

Now I can take the CLD exam wih confidence.Smiley Wink

 

Bill

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