While Loop default frequency

[Bobo083]

Hi guys,

Simple question:

What is the default frequency of a While Loop:

A) While Loop within a VI running under Windows

B) While Loop within a VI running under an RT Target

C) While Loop within a VI running under an FPGA Target

Thanks!

[Kyle97330]

I don't think you're going to get a helpful answer here because it's basically "as fast as it can, unless you tell it to slow down".

How about telling us why this information matters?

[JÞB]

LabVIEW is a Dataflow language.   This means as soon as all inputs are available to any node it will execute.

That includes loop iterations! So, a loop will execute as fast as the processor can execute it.  Period.  A "Greedy Loop" ( one that has no timing dependency to slow it down) will swallow up a whole CPU core.  

There is no default speed.

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[RTSLVU]

Not a simple question at all!

As there are many factors that can effect loop iteration time in any of the environments you listed.

My question to you is: Why do you need to know?

[BertMcMahan]

OP may be coming from a Simulink background or similar, where the "loop rate" is baked into the sim.

[altenbach · Accepted solution]

As has been said, the loop rate of an empty plain while loop is as fast as one CPU core can possibly spin it. This means it strongly depends on the hardware and not on the flavor of LabVIEW (Windows, RT, FPGA). An empty while loop seems quite useless (unless you are trying to heat your room), so the loop time will depends how long it takes to execute all code that is inside the loop. Even just measuring the loop time will falsify the results. Assuming the same algorithm, the speed depends on the implementation, i.e. also on the skills of the programmer. (If you are causing constant thread switching due to overuse of value property nodes or constantly calling the memory manager dues to constantly growing data structures, etc. your loop might be slower than you expect.)

Of course it also depends on what else is running. Placing a few dozen greedy while loops on a single diagram will have them fight for CPU and all will suffer.

In summary, unless this is a tight finite while loop (e.g. for a Newton-Raphson approximation), any toplevel while loop should have a reasonable wait to ensure that it runs the same on all hardware.

Note that there is also the timed loop (and even the single-cycle timed loop on FPGA). But you were asking about the regular while loop.

[Bobo083]

Thanks for your answer...

Few people were asking why i am interested how fast a While Loop spins ... the reason is that i was confuse with the clock speeds of the hardware and in my mind i was thinking that windows is slower than Real Time and Real Time is slower than FPGA 

[Yamaeda]

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@Bobo083 wrote:

Thanks for your answer...

Few people were asking why i am interested how fast a While Loop spins ... the reason is that i was confuse with the clock speeds of the hardware and in my mind i was thinking that windows is slower than Real Time and Real Time is slower than FPGA 

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RTs main benefit is that it's more determinate, which can be quite useful at times, else it's the same speed as normal windows (maybe a little faster due to less stuff running in the background, but that should be marginal).

FPGA is typically running at 125MHz, so quite a bit slower than a normal CPU (~30x), but it's highly parallell and has low memory latancy (a normal CPU can often have a 70 clock cycles cost to fetch data), so with the correct workload it can still be many times faster than a CPU for e.g. FFTs.