Which FPGA Module VIs are Supported by Higher Build Rates (80, 120MHz, etc)

[dclampp]

Hello,

I am using a PXI-7831 FPGA card with LabVIEW FPGA Module, and I'm trying to implement a Single Cycle Timed Loop in my VI. I am building it for 40MHz, and it compiles fine. I'm interested in bumping up the build rate up to 80MHz or even 120MHz. The user manual says that some SCTL-compatible VIs will not function at these higher rates, which I found out when I tried to compile.

I'm trying to find a list of the VIs that shows the cutoff band at which they can no longer be used in SCTLs. In particular, I'm looking to see just how fast I can use digital output and Look-Up Tables (1D) in SLTCs, or which other VIs can be considered speed limiters.

Thank you in advance!

-Derek

[Arun_V]

Hello Derek,

There is not really document I am aware of that tells the tick counts of each VI or function. But DO and Lookup table are SCTL compatible. DI, DO, Add, Subtract, Multiply, Memory read and Memory write are some of the functions that are SCTL compatible. AO, AI, Divide, Saturation arithmetic, DO (normal arbitration) are some of the functions that are NOT SCTL compatible.

I have also provided a link that talks about SCTL architecture.

http://digital.ni.com/public.nsf/websearch/38983B35676363AC86256F820062F0FE?opendocument&Submitted&&node=133020_US

Hope this helps.

Arun V
National Instruments

[dclampp]

Thanks Arun,

I have a followup question to this.  I have managed to rearrange  my code to meet a build rate of 80MHz while having a functional SCTL.  The period of the SCTL is of importance to me, so I'm curious what is the accurate measurement of the period (or frequency) of the loop.  When I build for 80MHz, and it meets that by building at 84.4869553MHz roughly; does the SCTL loop at 80MHz or at 84.4... MHz?  Does it loop at the target build rate or the actual build rate? 

Thanks!

-Derek

[Peter_Bham]

Hello,

I would like to post a related question on this thread. 

I am using an NI PCI-7831R for AI and AO.  Inside a while loop I am using the AI block wired to a shift register, the shift register is wired to the AO.  The only other function is a tick counter wired to a subtract and a shift register to measure loop rate.  Both of these examples are scaled down versions of examples from the NI tutorials.  I have no timing or other functions running in the loop.

My question is:
Why when I raise the speed of my FPGA target and rebuild does my loop tick count increase (the tick counter is set for tick count not mSec or uSec)?  At 40MHz it is about 130, at 120MHz it is about 500.  On a scope monitoring AI and AO I have a constant 8 uSec shift independent of the FPGA target speed.  When I rebuild each time I verify that the unit was able to meet the time constraints.

How do I calculate the length of 1 tick?  Is it based on the Targeted speed or the actual build rate?

Thanks,
Peter

[Doug M]

Hi Peter,

You submitted this question also via email.  Please submit questions in only one place so we don't duplicate our response efforts -- thanks!  For anyone else's benefit, the answer I gave was:

"Regardless of your FPGA clock rate, the A/Ds and D/As take a finite amount of time to execute.  The 7831 is speced at 200 kHz for AI.  at 130 ticks you are a""ctually running at 300+ kHz, so the A/Ds mays not even settling completely.  The 8 uSec shift sounds about right since you are using a shift register so there will be a shift of one iteration between AI and AO, which may look like a bit more on a scope depending on the delay between when the signal hits the A/D versus if you are looking at it on a high speed scope.

Non analog tasks will run faster at faster FPGA clock rates."

Also, analog input loops should always be timed rather than letting the loop run as fast as possible.

[Peter_Bham]

Doug,

Sorry about the double posting.

Any suggestions on how to delay the signal by almost one period.  The application I am using requires the phasing to be better than the 8uSec.  I have tried shift registers, this method is dependent on the overall timing in my loop.  In general,  how do you sync the input and output phasing.  Thanks for the assistance.

Peter

[Doug M]

Peter,

I don't know that you are going to be able to get much more accuracy than what you are seeing as far as making analog output and input in phase.  The way to get the least delay and most efficiency that I know of between AI and AO is to use the method shown in the attached screen snippet. Hope this helps!