LabVIEW
What does Sigle Cycle Timed Loop mean?
The Single Cycle Timed Loop (SCTL) is a new programing structure in the LabVIEW FPGA module 1.1. It is similar to a While loop, but all the code inside the SCTL executes within a single cycle of the FPGA clock (25 ns). Because of this advanced behavior of the SCTL there are some limitations to the code that can be used inside of the SCTL. If you do not adhere to these limitations you will get an error during the compile process.
Partial list of limitations:
- You can not use any loop structures (While, For, SCTL) inside of a SCTL.
- You can not use analog input and output functions inside the SCTL.
- You can not use any complex functions (such as Quotient and Remainder) that require more than one clock cycle to complete.
- The total extent of the c
ode used inside the SCTL must be simple enough that the compiler can fit it inside of one clock cycle.
Things you can and should do:
- You can use Case Structures inside of a SCTL to build a single cycle state machine.
- You can use shift registers and pipeline your code such that you break up your code among multiple iterations of the SCTL.
- Digital I/O and memory read and write functions are best used through a shift register. For excample, the value coming from a digital input is directly wired to a shift register on the right side of the loop. The data is then processed in the next iteration of the SCTL by taking the value from the shift register on the left side of the loop.
Christian L
NI Consulting Services
Partial list of limitations:
- You can not use any loop structures (While, For, SCTL) inside of a SCTL.
- You can not use analog input and output functions inside the SCTL.
- You can not use any complex functions (such as Quotient and Remainder) that require more than one clock cycle to complete.
- The total extent of the c
ode used inside the SCTL must be simple enough that the compiler can fit it inside of one clock cycle.
Things you can and should do:
- You can use Case Structures inside of a SCTL to build a single cycle state machine.
- You can use shift registers and pipeline your code such that you break up your code among multiple iterations of the SCTL.
- Digital I/O and memory read and write functions are best used through a shift register. For excample, the value coming from a digital input is directly wired to a shift register on the right side of the loop. The data is then processed in the next iteration of the SCTL by taking the value from the shift register on the left side of the loop.
Christian L
NI Consulting Services
