Vivado 2013.4 compilation error

[SaileshK]

Hey Amuri,

How often does this error occur? Is it intermittant, or does it happen every time you try and compile? Are you trying to compile multiple FPGAs in parallel?

[Amuri]

Yes, it happen all times. I almost give up using NI. I have three FPGA VIs for my three MyRios in my system.

[Intaris]

Long shot....

If you have a clock constraint for a custom CLIP which links to a clock you're actually NOT using in your design, it can lead to this error.  I have run into this int he past and it took me a while to find out where the problem originated.

Low chance of being correct, but in the absence of other alternatives....

Oh, actually, forget that, I see your error occurs at the Generating IP stage....

[BdogTheWatchdog]

Hey Amuri,

Feel free to provide your FPGA VIs if you'd still like to investigate this issue and we can see if it's something with those. Do you get the same behavior with trying to compile a new/mostly blank VI?

Bdog

[isaacvega]

Bump again

[ybalam]

isaacvega,

Are you having a similar issue? If it's the same, then can you provide us with your FPGA code, information about your environment, and the errors you're getting? Also, are you able to compile a mostly blank VI--maybe something that just adds two numbers together? 

If what you're experiencing is different enough from the original post, I might recommend starting a new thread to get fresh eyes on it as well.