Virtual Bench Trigger Out

[AlexanderKhodarev]

Hi,

I have a question about Virtual Bench trigger output. I want to generate waveform and set output trigger in such a way that it triggers every cycle of the waveform. It seems that solution is straightforward: generate signal, start generation, configure trigger output to "FGEN start". The problem is that it doesn't work - signal is generated but there is no trigger output.

Has anyone any experience with Virtual Bench generating output trigger?

measured signals. Triangle itself is generated but there is no trigger.

[crossrulz]

You have a race condition between the setting up of the trigger and starting the starting of the waveform.  However, still don't think it will retrigger on every cycle.

[AlexanderKhodarev]

i actually tried all combinations

1) initialize signal generation, init trigger, start signal generation

2) init sig gen, start siggen, init trigger

3) init trigger, init siggen, start siggen

also tried "reset" flag at initialization (checked both TRUE and FALSE).

effect is always the same - there is a signal and there is no trigger, not even one time.

Moreover as i understand it - there can be no race conditions - i should be able to start signal generation and assign trigger in any sequence. Sure i might miss few triggers, but at this point i just want to get any trigger at all.

I also checked that line is physically connected. When i initialize trigger line i see that signal goes to 2.8V. However once i get to VI which sets trigger line to FGEN signal goes to 0 and thats it.

[AlexanderKhodarev · Accepted solution]

After some investigation: trigger signal is correctly generated at each cycle of waveform. However it is just about 25ns wide so it's near impossible to see using RT DIO.