I suspect that one reason that they haven't been forth coming about this (and they have been asked since its release a number of years ago) may be that there are proprietary issues on either the Xilinx or the LabVIEW or both sides. It would be interesting to import the VHDL into one of the design environments to see how optimized the code it, and allow tweeking, but the primary target that they are marketing this to are non-VHDL pros.
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