Using the Analog Period VI

[bees1995]

Hi all,

I'm currently designing a VI to use in an FPGA that measures the period of an analog signal. To do this, I am using the analog period measurement express VI. I want it to take 1 tick to run, but currently it is taking 17. I have tried to import the express VI as a subVI and then place that piece of code within the VI, but I can't get it to work as anticipated. 

Can anyone help me understand why the express VI takes 17 ticks to execute, or how to get the express VI working as a piece of code within another VI?

Thanks,

Dan

[crossrulz]

Did you put it inside of a Single Cycle Timed Loop?

[bees1995]

So the analog period express VI is a SCTL once you extract it, and I'm not keen on placing a loop within a loop.

[bees1995]

My question is basically how does the express VI work when it is unpackaged? As far as I can tell, all it is looking for is a zero crossing. However, when I try and use a zero crossing VI, my results are not as smooth. Is there an additional function that I am not aware that this VI uses? I want to use this express VI within an SCTL but it doesn't let me unless I unpackage the VI, hence why I want to understand how it works so I can manipulate it for use in an SCTL.

[bees1995]

My question is basically how does the express VI work when it is unpackaged? As far as I can tell, all it is looking for is a zero crossing. However, when I try and use a zero crossing VI, my results are not as smooth. Is there an additional function that I am not aware that this VI uses? I want to use this express VI within an SCTL but it doesn't let me unless I unpackage the VI, hence why I want to understand how it works so I can manipulate it for use in an SCTL.

[BdogTheWatchdog]

Hi Bees,

In the subVI, the logic inside the SCTL will run within one click tick; it's likely that the controls and indicators in the Express VI, and possibly the benchmarking method, are adding to the tick count. 

Bdog