Using Xilinx CORE IP for Multi-sample Clip

[nkmath]

Hello,

I am using an NI5761 FAM paired with a 7965R FPGA module to perform real-time processing of analog data. I was hoping to utilize digital filters, and to start, would just like to include a low and high pass filter to separate the AC and DC components. 

After doing some searching I stumbled upon this helpful presentation, 

ftp://ftp.ni.com/pub/branches/northern_region/nidays2011/dsp_in_lv_fpga_with_flexrio.pdf

which concludes that the most effective/efficient way to do this is through the Xilinx CORE Generator IP. However, it appears that this is set up for the "Single Sample CLIP" configuration where there is 1 sample for each clock cycle . Is there documentation on a way to generalize the Xilinx CORE IP functions for use in the "Multi Sample CLIP" (i.e. 2 samples/clock cycle)? From what I see these Xilinx functions only accept 1 sample per clock cycle. 

The code that is downstream of where the filter would be is already set up for the Multi Sample CLIP. Ideally it would nice to not have to redesign the code to include the filter. Furthermore, there would most likely be timing restrictions if I double the SCTL rate by using the Single Sample CLIP. 

I imagine one solution may be to operate using the single sample CLIP with two SCTL loops. The first loop operates at the sampling frequency (250 MHz), and extracts/filters the input data. The output from the filter is then passed to a second loop ( with half the frequency of the first ) via a Target scoped FIFO. This would allow the code architecture to stay the same.

In any case, before I try anything I was hoping to get input from the community and see if there is a more straightforward or accepted solution to this issue. 

Thanks for any help! 

[Jorr-El]

Hi nkmath,

Is there a specific reason you want to use the multiple sample CLIP instead of the single sample CLIP other than your downstream code?

I also found an example program that might give you some more insight into using the Xilinx CORE Generator for FIR filtering in LabVIEW:

Polyphase Interpolation FIR Filter on FPGA with DFD and Coregen

https://forums.ni.com/t5/Example-Program-Drafts/Polyphase-Interpolation-FIR-Filter-on-FPGA-with-DFD-...

However, National Instruments does not maintain any documentation or example programs on how to use the Xilinx CORE Generator for use with our FPGA or FlexRIO hardware. If you'd like more information and guidance regarding the use of the Xilinx CORE IP functions, you might be more successful taking a look at the Xilinx Community Forums.

[BauerPower · Accepted solution]

Hi! If you're just looking to do digital filtering, the Xilinx FIR Compiler included in LV FPGA does support multiple-spc input. We also have a collection of DSP functions in our "DSP IDL" which support 1, 2, 4, 8, and sometimes 16 spc. You should be able to configure it as such in the configuration screen once you drop it on the block diagram. 

[nkmath]

Hello,

Ah great, I simply needed to look a bit harder then. I have not had time to implement this (and won't for some more time) but in principle that should work! Thanks for the advice. I'll mark it as the solution for now, and if for some reason it doesn't work when I find some time to work on it, I'll update this thread. 

Cheers

Nolan M.