Using VI Scripting to generate FPGA VI

[wiebe@CARYA]

---

@Intaris wrote:

---

wiebe@CARYA wrote:

---

FPGA Arrays are OK if they're small, but conceptually (sorry if I edited that in after you replied) FPGA memory would work as well.

---

Ooh, sneaky. 😋

The thing with Arrays is they take not only space for the array itself, but rotating and so on take increasingly more resources the larger the array gets (i.e. the number of elements in the array as well as the size of each element). 

---

But you don't need to rotate the array.

Keep a pointer of the element you set, and increase the pointer. If it's bigger than the array size (preferably n**2, so you can AND the size) start at 0... Getting a delay of 10 is simple by getting (pointer-10) AND size.

[Intaris]

Yeah, but then the increasing cost of Array Subset that I linked to earlier comes into play.

So either Rotate is required or dynamic index is required.... Both get expensive fast for arrays.

unless there's another way via arrays?

[wiebe@CARYA]

---

@Intaris wrote:

Yeah, but then the increasing cost of Array Subset that I linked to earlier comes into play.

So either Rotate is required or dynamic index is required.... Both get expensive fast for arrays.

unless there's another way via arrays?

---

Why do you need Array Subset? Index Array would do. Or a read from the memory of course.

[Intaris]

Zes of course, you're right. Less costly than subset, but still scales badly with array depth.

Same thing applies to Rotate, Subset, Index, Insert, Replace.....

[David-A]

If you're looking for a variable delay buffer the FlexRIO driver installs one. Its used in the default personality FPGA vi for some of our Integrated IO FlexRIO devices, but any FPGA device can use them.

<LabVIEW>\instr.lib\FlexRIO\API\FPGA\v1\Variable Delay.vim

There's also a circular buffer in instr.lib\FlexRIO\API\FPGA\v1\subVIs but it sounds like the variable buffer will get you what you want. 

[jiangliang]

Thank you very much for your suggestion, I'll take a look on this.

[jiangliang]

Thank you, that's what's I been looking for:) One more thing, If I actully using that much Delay element, the LV IDE is really not that responsive, it hangs there every once in a while. even I set realtime error check to level 0 in settings.

[jiangliang]

Thank you for your advice.

I actully need to access certain values at each of these delay function, say I need data of i, i(-22), i(-43), i(-335)... all the way down to i (-16383), at the same time, I'm updating the whole serial at 400MHz, so there is really not a easy job to do.

I assume if I set delay to each fixed number instead if using dynamic delay should help me on getting more performance, am I right?

[jiangliang]

On My! I always thought this delay function is a packed version of "RAM-based Shift Register" in Xilinx IP.

And you point here it doesn't using BRAM or for that?

[David-A]

I've not had any issues with IDE responsiveness when using this library.

You won't have access to anything but the oldest element. Its functionally a variable length FIFO. If you need random access you'll need to create a copy of the library and modify it. 

When using certain LVFPGA primitives (like feedback nodes) the compiler will sometimes use flip flops, sometimes LUTs, sometimes BRAM. The LVFPGA compiler does a good job of determining what is the optimal resource and instantiates it for you. In this case, if the maximum length of the buffer is of a certain size (I think anything greater than 32 or 64 elements, but don't quote me on that) it will probably use BRAM.