Hello Everyone,
I want to transmit a U32 value from the FPGA to a real-time application running on a PXI controller in the same chassis as my FPGA. I want to do this with as little latency as possible.
I thought this could be achieved by creating, writing to, and reading from a 1-element Target-To-Host DMA FIFO that I defined in my project.
At the time I believed I could perpetually write to this FIFO from the FPGA and it would overwrite the element like a circular buffer. Then, a piece of real-time software could read the newest value sitting in the FIFO, on demand.
That doesn't seem to be the case. As I try to read the FIFO from a real-time software component, the DMA transfer seems to operate in short bursts, stop working, then operates correctly again after some time. This continues throughout runtime.
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The FPGA writes to the FIFO every 20 uSec, on average. (Data is dependent on the performance of a device on the other end of a UART interface)
The real-time software reads 1 element form the FIFO every software frame, or 2ms.
Am I approaching this correctly?
What I have tried:
1. Using the FPGA Interface library to read the data from a control on the FPGA VI's front panel. This works as expected, but I only did this to verify my design. I'm concerned this approach introduces a lot of latency.
2. Flushing the FIFO at the start of my duty cycle (2uSec after writing to the FIFO). This results in identical performance (bursts of the DMA working, then not working, and working again).
I assume the DMA implementation would be faster, and I would really like to get this working.
Could someone explain what I'm not understanding about the FIFO/DMA approach?
If DMA is not an option, could someone suggest a software approach to make this U32 value available on demand by a PXI controller (in the same chassis as the FPGA) with as little latency as possible?
Thank you kindly,
-Chrs
